VDB-NOTES: real hardware (Jaton CL-GD5434 + MACH130 CPLD + 3x Bt477 RAMDAC)

Operator documented the physical VDB + companion card: Jaton KY2-JAX-CVGA54PCI
(Cirrus CL-GD5434) feeds a 26-pin feature-connector ribbon to an AMD/Lattice
MACH130-15JC CPLD (the ISA 0x300-0x31A port decoder + hardwired byte-lane
splitter), which drives 3x Brooktree Bt477KPJ80 RAMDACs -> one VGA stream to
the color radar + a DB25 fan-out to the 5 mono MFDs. Confirms the RE (3 DACs =
3 palette groups; Bt477 6-bit DAC = the driver's shr al,2). A component tied in
parallel to the PC front-panel reset (remote reboot or VDB known-state on
reset) is under operator research. Also: RP uses the FULL 640x480 on all 6
displays (so our top-strip decode = a framebuffer READ bug, stride/page, not
sparse RP content).

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

emulator/VDB-NOTES.md

@@ -118,17 +118,41 @@ Aux palette side-by-side; the ramp/channel structure shows the bit layout);
 (d) confirm the low/high byte order and the 640x480 vs a smaller gauge region
 (top-strip content hints RP may draw gauges in fewer rows).
 
-## Physical-sample verification checklist (have the board + Cirrus card)
+## Physical hardware (documented from the operator's sample, 2026-07-10)
 
-Photograph and record for the archive:
+CONFIRMS the reverse-engineering below the chip level:
-- **Splitter board**: the port-decoder PAL/GAL (mark/part#) at 0x300-0x31A;
+
-  the THREE RAMDAC chips (part#, are they real Bt476/Bt478-class or a Cirrus
+- **Companion video card**: **Jaton KY2-JAX-CVGA54PCI** — a legacy PCI Local
-  DAC?) and how their pixel-mask/addr/data pins map to 0x302/0x30A/0x312; the
+  Bus VGA card, **Cirrus Logic CL-GD5434** chipset. Renders the cockpit gauges
-  high-color-divider logic tied to 0x319/0x31A; the feature-connector tap.
+  (640x480x16, VBE 0x111) and feeds the pixel stream to the VDB via a **26-pin
-- **Octopus cable**: pinout — which of the 3 head outputs feeds which of the
+  ribbon off the VGA Feature Connector**.
-  6 cockpit displays (confirms the pentapus win5-9 + radar mapping).
+- **The splitter brain**: **AMD/Lattice MACH130-15JC** CPLD — EE-CMOS, 64
-- **Companion Cirrus Logic card**: exact chip (CL-GD54xx?) + BIOS, to pin the
+  macrocells, 15 ns max prop delay, 84-pin PLCC (2nd-sourced by Rochester
-  640x480x16 mode/pitch and the feature-connector timing the divider assumes.
+  Electronics). This is "Adam's port decoder": it CONSUMES the feature-connector
-- Any onboard ROM/PAL dump (like the RIO EPROM) for full preservation.
+  video stream AND takes instructions from the **ISA bus** (the 0x300-0x31A
+  register file — palette loads, masks, and the 0x319/0x31A high-color clock
+  divider). It does the byte-lane split in hardwired logic (same for BT and RP).
+- **The three DACs**: **3x Brooktree Bt477KPJ80** RAMDACs (256-entry, 6-bit/
+  channel, 80 MHz) = the three palette groups Secondary/Aux1/Aux2. The Bt477's
+  6-bit DAC is exactly why the driver does `shr al,2` (8->6) on palette writes.
+  Output routing (confirms the head map): **one Bt477 -> a VGA stream to the
+  color RADAR display** (= Secondary/0x302); the **other two Bt477s -> a DB25
+  connector that fans out to the 5 monochrome MFDs** (= Aux1/0x30A R,G = 2
+  lower MFDs, Aux2/0x312 R,G,B = 3 upper MFDs; 5 mono wires total, one channel
+  unused). The DB25 fan-out is the "octopus/pentapus" cable.
+- **Reset-tie component**: a part wired in PARALLEL with the PC's front-panel
+  RESET switch — either a remote-reboot path OR a means to force the VDB into
+  a known state when the PC is reset (so the CPLD/DACs re-init cleanly).
+  OPERATOR RESEARCHING. (Plausible: the CPLD needs a hard reset synchronized
+  with the host, since it has no software reset in the 0x300-0x31A map -- only
+  clock on/off; a reset tie guarantees the splitter isn't left mid-state.)
+
+### Still worth capturing for the archive
+- Photos of each chip + the board silkscreen; the DB25 pinout (which pin ->
+  which MFD) and the 26-pin feature-connector ribbon pinout.
+- Whether the MACH130 JEDEC fuse-map is readable (a MACH130 can often be
+  read back unless secured) -- that IS the splitter logic, the ultimate
+  ground truth, and preservable like the RIO EPROM.
+- The reset-tie circuit trace (operator's follow-up).
 
 Related: [[vdb-three-vga-head-decode]], [[tesla-cockpit-emulator-state]].