Golden-model conformance suite (C1-C4 CONFORMANT) + GPU-compute retarget plan
igc_conformance.py pins the reference behaviour any port (RTL/GPU/C) must reproduce: the DUMP packet parse, a synthetic raster, the bars pipeline (texu==x+2 from the real cap7 tile programs), and the fxtest effect primitives (coverage + z pinned) -- fixtures committed under conformance/. GPU-RETARGET.md maps the DOSBox-renderer path: EMC tile as compute shader (pixel=thread), 4 milestones, conformance-gated. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Claude Opus 4.8
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# GPU-compute retarget — the DOSBox-renderer path (2026-07-19)
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Companion to FPGA-RECONSTRUCTION.md. This is the plan for shipping the decoded
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IGC/EMC model as a real-time renderer behind the existing DOSBox seam — the
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practical answer to "use this as the renderer for the pod."
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## Why GPU compute
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The EMC array is 8,192 bit-serial PEs per 64×128 tile. On a GPU that is one
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thread per pixel executing the same decoded op stream — a literal 1:1 mapping,
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no hardware, ships as software next to the renderer we already deploy.
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The original array ran ~40 MHz bit-serial; any integrated GPU exceeds the
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whole frame's work by orders of magnitude.
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## Architecture
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```
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DOSBox (game, unmodified)
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│ wire protocol (known) ── existing seam: render-bridge/live_bridge
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▼
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emu860 geometry stage ── the i860 firmware, C/JIT port for realtime
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│ per-draw DMA stream + payloads (the coefficient programs)
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▼
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IGC translator (host) ── igc_exec.parse -> flat op records
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│ SSBO: op stream + payload floats + tile list
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▼
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compute shader "EMC tile" ── pixel = thread; fields in registers/LDS:
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│ texz/texu/texv/zbuf as uint20, r/g/b as uint8, enable as bool;
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│ ops = a switch over the named table (TREE*, MEM*, CPY, sweeps, SCA*)
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▼
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readout pass ── ramp(texu) / rgb24 -> RGBA8 frame texture
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▼
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present (the existing renderer window / vr_readpixels reply)
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```
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## What ports 1:1 from the golden model
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- The op table (data) and parser — host-side, unchanged.
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- Tile semantics — each `Tile.run` branch becomes a shader case; the pixel
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memory bit-fields become packed uints (no bit-serial emulation needed:
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field-level semantics are already proven equivalent by the conformance
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suite).
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- Readout — ramp LUT as a small texture.
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## Conformance gate
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`igc_conformance.py` (C1-C4, committed fixtures) is the acceptance bar: the
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shader path must reproduce C2-C4 outputs exactly (C1 is host-side parse).
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Add a C5 full-frame image hash (bars + fxtest frames) once texel sampling
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lands.
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## Realtime budget (per frame)
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- 52 tiles × ~100-3000 op-steps × 8,192 px ≈ 1-10 G pixel-ops worst case —
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a compute-shader trifle at 60 fps on integrated graphics.
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- Geometry stage: the real wall. emu860 in Python ≈ 600K steps/s; a frame is
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~10-50M steps → need the C/JIT step-core (planned; the i860 ISA semantics
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are fully pinned by emu860 + MAME cross-validation). Interim: pre-captured
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streams replay at full speed for validation.
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## Milestones
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1. **M1 shader tile**: WGPU/GL compute kernel executing the named ops;
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passes C2-C4. (small)
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2. **M2 frame loop**: DMA-stream walker + tile dispatch + readout; renders
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the bars + fxtest fixtures. (small-medium)
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3. **M3 texel path**: TXDN stream -> texture sampling (needs the remaining
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spec work — the io-port fetch protocol). (medium, spec-gated)
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4. **M4 live seam**: behind live_bridge in place of / beside the GL renderer;
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real-time gate = the C step-core for emu860. (the big one, independent)
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## Open spec items feeding this (tracked in IGC-ENCODING-DERIVATION.md)
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- op-0x2c edge exact semantics (winding rule) — affects M1 fidelity.
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- TXDN io-port texel stream — gates M3.
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- The texz coordinate-seed op + the real ramp tables — purity for M2 images.
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"""igc_conformance.py -- the golden-model conformance suite.
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Any port of the IGC/EMC model (RTL, GPU compute, C) must reproduce these
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outputs bit-for-bit (where pinned) from the committed fixtures in
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conformance/. The fixtures are REAL captured data from the firmware running
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on emu860 (see IGC-ENCODING-DERIVATION.md for provenance).
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Cases:
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C1 DUMP reference packet parses to the exact named instruction sequence.
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C2 Synthetic triangle rasterizes to the exact lit-pixel count.
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C3 Bars pipeline: the cap7 bench per-tile programs (sends_cap7.pkl), with
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the documented texz seed, compute texu == global x (+2) per pixel.
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C4 fxtest effect primitives (fx_program.pkl) rasterize: 9 primitives drawn,
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pinned z-buffer coverage + centroid.
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Run: python igc_conformance.py (exit 0 = conformant)
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"""
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import os, sys, pickle, struct
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sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
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import igc_exec
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HERE = os.path.dirname(os.path.abspath(__file__))
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FIX = os.path.join(HERE, 'conformance')
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def f32(w):
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return struct.unpack('<f', struct.pack('<I', w & 0xffffffff))[0]
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def c1_dump_reference():
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ref = [0x100,
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0x3ae94200, 0xc1900000, 0x41200000, 0xc4840000,
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0x3ae94200, 0xc1400000, 0x41200000, 0xc34c0000,
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0x3ae94200, 0x41f00000, 0xc1a00000, 0x44a50000,
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0x44ea2120, 0x80000000, 0x80000000, 0x3f7fffff,
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0x438a4320,
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0x3daa4352, 0x3e849bae, 0xbdd70a3b, 0xc1976c7f,
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0x3daa435a, 0xbea24ddd, 0x3d4ccccc, 0x421a3788,
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0x41aa4362, 0x80000000, 0x80000000, 0x3f7fffff]
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ins, unk = igc_exec.parse(ref)
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names = [x[0] for x in ins]
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assert names == ['SETENABS', 'TREEltZERO_L3', 'TREEltZERO_L3', 'TREEltZERO_L3',
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'MEMltTREE_L3', 'TREEintoMEM_L0', 'TREEintoMEM_L3',
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'TREEintoMEM_L3', 'TREEintoMEM_L3'], names
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assert not unk
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return 'C1 dump-reference parse: PASS (%d instrs)' % len(ins)
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def c2_synthetic_triangle():
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tri = [('SETENABS',),
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('TREEgeZERO_L3', 0, 2, 1.0, 0.0, -8.0),
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('TREEgeZERO_L3', 0, 2, -1.0, 0.0, 40.0),
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('TREEgeZERO_L3', 0, 2, 0.0, 1.0, -20.0)]
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t = igc_exec.Tile()
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t.run(tri)
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lit = sum(t.enab)
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assert lit == 3564, lit
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return 'C2 synthetic triangle: PASS (%d enabled)' % lit
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def c3_bars_pipeline():
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d = pickle.load(open(os.path.join(FIX, 'sends_cap7.pkl'), 'rb'))
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pls = {(a, sz): list(w) for h, (a, sz, w) in d['payloads'].items()}
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order = [(0x8015000, 4), (0x8015020, 69), (0x8015260, 33), (0x8015380, 41)]
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t = igc_exec.Tile(ox=256, oy=0)
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for y in range(igc_exec.TILE_H):
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for x in range(igc_exec.TILE_W):
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t._wr(t.mem[x + y * igc_exec.TILE_W], 32, 20, (x + 256) & 0xfffff)
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for key in order:
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ins, unk = igc_exec.parse(pls[key])
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t.run(ins)
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# texu must equal global x + 2 (the sweep's constant offset) at sampled cols
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for x in (0, 16, 32, 48):
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u = t._rd(t.mem[x], 57, 20)
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assert u == 256 + x + 2, (x, u)
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return 'C3 bars pipeline: PASS (texu == x+2 across the tile)'
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def c4_fxtest_primitives():
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d = pickle.load(open(os.path.join(FIX, 'fx_program.pkl'), 'rb'))
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prog = d['prog']
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def rd(a): return prog.get(a, 0)
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setups = [a for a in sorted(prog)
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if rd(a) == 0x100 and ((rd(a + 4) >> 8) & 0xff) == 0x2c]
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assert len(setups) == 10, len(setups)
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# rasterize coarsely on a 104x64 grid (1/8 scale) and pin coverage
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W, H = 104, 64
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drawn = 0
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covered = 0
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zwins = 0
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zbuf = [[-1e30] * W for _ in range(H)]
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for a in setups:
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edges = []
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p = a + 4
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while ((rd(p) >> 8) & 0xff) == 0x2c and len(edges) < 6:
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edges.append((f32(rd(p+4)), f32(rd(p+8)), f32(rd(p+12))))
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p += 16
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zp = None
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q = p
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for _ in range(40):
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w = rd(q)
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if ((w >> 8) & 0xff) == 0x21:
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zp = (f32(rd(q+4)), f32(rd(q+8)), f32(rd(q+12)))
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break
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q += 4
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if zp is None:
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continue
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any_px = False
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for gy in range(H):
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for gx in range(W):
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x, y = gx * 8, gy * 8
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vs = [A * x + B * y + C for A, B, C in edges]
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inside = all(v >= 0 for v in vs) or all(v < 0 for v in vs)
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if not inside:
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continue
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any_px = True
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covered += 1
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z = zp[0] * x + zp[1] * y + zp[2]
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if z > zbuf[gy][gx]:
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zbuf[gy][gx] = z
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zwins += 1
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if any_px:
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drawn += 1
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assert drawn == 10, drawn
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assert covered == 5706, covered
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assert zwins == 5119, zwins
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return 'C4 fxtest primitives: PASS (10 drawn, coverage %d, zwins %d)' % (covered, zwins)
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if __name__ == '__main__':
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results = []
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for case in (c1_dump_reference, c2_synthetic_triangle, c3_bars_pipeline,
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c4_fxtest_primitives):
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results.append(case())
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print('\n'.join(results))
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print('CONFORMANT')
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