This is the final stage in silicon — and it now runs in software. The
+ PXPL5 IGC is a region rasteriser: the screen splits into
+ 64 × 128 tiles; every pixel carries a 26-byte bit-memory and an enable bit; all
+ pixels evaluate one linear tree in lockstep —
+ eval_ltree(x,y,A,B,C) = (int)(x·A + y·B + C). A triangle becomes
+ three edge trees into the enable register, then Z and R/G/B planes
+ interpolated per pixel and z-buffered in pixel memory (IGCOPS.C).
+ Fed the captured surface, the model lights the tiles below and renders pixels that match our
+ reference rasteriser to within edge anti-aliasing — the array reproduced faithfully.
+
+
+
+ the object's footprint across the array — 18 of 50 tiles lit,
+ each a 64×128 region of pixel processors
+
+
+
pixel memory · 26 bytes = 208 bits
+
+ Z · 24bR·8G·8
+ B·8enable + working bits
+
+
+
three edge trees → the enable register (the inside test)
+
Z / R / G / B are planes, evaluated per pixel by the linear tree
+
z-buffer via MEM2geMEM2; every write gated by enable
+
output read back out of pixel memory → framebuffer
+
validated pixel-faithful to the reference — ~1%, at edges only
+
+
+
+
What this is not, yet: a decode of the compiled
+ bit-serial micro-code the DMA actually ships (§02, right). That binary encoding is still
+ undecoded, and it is how the ground and sky — which carry no stored vertices — reach the array.
+ This is the array's computational model: the pixels that micro-code would produce.
+
+
+
+
06 What it took to get here
The i860 core was corrected against the toolchain's own assembler output
and MAME's validated i860 model. A selection of the load-bearing fixes:
@@ -299,15 +363,16 @@
Real PXPL5 IGC opcode stream emitted and decoded (SEND / TILE / FLUSH)
Geometry binned into 191 screen regions
Object recovered and shaded — a 9×5 height-field surface, lit by the firmware's own normals (above)