Phase 2 progress: boot handshake + i860 download solved; FIFO path mapped

The VPX responder device now drives production BattleTech v4.10
through the full transputer/i860 boot, far past the Phase 1 wall:

- iserver boot handshake solved: feeds 3 well-formed 'version' (tag 42)
  iserver requests, satisfying startup_handshake()'s 3 transactions.
- i860 download solved: parses the outbound framed renderer messages
  (vr_860args/code/data/bss) and absorbs them, staying byte-aligned.
- echo-action reply model validated against board source
  (VRENDER/VR_REMOT.C reply() echoes the received action); device
  tracks and echoes the last outbound action generally.

Remaining sub-protocol identified and characterized: after i860 boot
the host switches to a FIFO fast path (OUTSW.ASM: 0x40 tag + REP OUTSW
16-bit words to FIFO port 0x154/0x155, gated by ok_to_fifo at 0x160).
The current build stops at velocirender_sync because the device only
implements the slow byte path. PHASE2-PROGRESS.md documents the exact
next steps (FIFO transport + render loop -> Phase 3 OpenGL backend).

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

emulator/respond.conf

@@ -0,0 +1,26 @@
+[sdl]
+output=opengl
+[dosbox]
+memsize=32
+machine=svga_s3
+[cpu]
+core=normal
+cputype=pentium
+cycles=20000
+[serial]
+serial1=disabled
+serial2=disabled
+[autoexec]
+mount c "image"
+c:
+set L4CONTROLS=RIO,KEYBOARD
+set L4TIMER=
+set BLASTER=A220 I5 D1 H5 P330 T6
+set VIDEOFORMAT=svga
+set TEMP=c:\
+set DPLARG=/tranny~.\vrendmon.btl~/i860~.\vrnostex.mng~/device~0x150~/video~svga~/pipes~1~/qual~0x14~/system_tex~0~
+32rtm.exe -x
+btl4opt.exe -egg test.egg
+32rtm.exe -u
+echo RESPOND-DONE
+pause