RP's cockpit displays decoded near-empty (top-strip only, a copy off-screen at
VRAM 0x100000) while BT's were full. Root cause was NOT the VDB decode (byte
split/palettes/stride all correct, proven by BT) but an SVGA bank-switch
GRANULARITY mismatch: RP's REL410/RP/GAUGE/L4GAUGE.INI [640x480x16] used
granularityInKB=4 vs BT's 64 on the same STB Horizon+ (CL-GD5434). DOSBox-X's
CL-GD5434 bank emulation handles 64KB granularity (BT full) but mishandles the
4KB-granular paged gauge writes, scattering them off-screen.
FIX (config, no rebuild): RP L4GAUGE.INI granularityInKB 4->64 (matches BT,
same card). VERIFIED live: VRAM content scan went from 0x0+0x100000 (top-strip
+ off-screen) to the FULL framebuffer 0x0..0x90000 populated; radar +
upper-center MFD confirmed correct, rest under reference check.
Also commits the VDB diagnostic tooling that found it (vpxlog.cpp, all
default-off): VDB_SCAN (VRAM content locator -- decisive), VDB_PALDUMP,
pixel-mask value logging, VDB_REALSTRIDE + live mode/stride/start logging,
VDB_BASE read-base override, VDB_APPLYMASK DAC-mask honoring. Full writeup in
VDB-NOTES.md.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Operator documented the physical VDB + companion card: Jaton KY2-JAX-CVGA54PCI
(Cirrus CL-GD5434) feeds a 26-pin feature-connector ribbon to an AMD/Lattice
MACH130-15JC CPLD (the ISA 0x300-0x31A port decoder + hardwired byte-lane
splitter), which drives 3x Brooktree Bt477KPJ80 RAMDACs -> one VGA stream to
the color radar + a DB25 fan-out to the 5 mono MFDs. Confirms the RE (3 DACs =
3 palette groups; Bt477 6-bit DAC = the driver's shr al,2). A component tied in
parallel to the PC front-panel reset (remote reboot or VDB known-state on
reset) is under operator research. Also: RP uses the FULL 640x480 on all 6
displays (so our top-strip decode = a framebuffer READ bug, stride/page, not
sparse RP content).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Comprehensive VWE Video Display/splitter Board writeup: what it is (dumb ISA
splitter tapping the companion Cirrus Logic SVGA feature connector), the
definitive I/O register map from L4SVGA16.ASM (Secondary 0x302 / Aux1 0x30A /
Aux2 0x312, each +0 mask/+1 read/+2 write/+3 data, 6-bit DAC; clock divider
0x319 off / 0x31A on), the byte-lane split (low byte->Secondary, high
byte->Aux1/Aux2 -> separate VGA heads -> octopus cable -> 5 mono MFDs + color
radar), the driver's bitMask+channelEnable CLUT-build trick that packs multiple
displays into one framebuffer, the pixel-mask flash + Secondary-only fade, our
emulation, the OPEN RP decode problem, and a physical-sample verification
checklist (port-decoder PAL, 3 RAMDACs, octopus pinout, Cirrus chip id).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
CydandClaude Fable 5