// nicked from output of PGC Rel 1.4 -opt 2 .text .align 8 .text //{{{ register allocation // // r1 return address // r2 sp // r3 frameP // r4 .. r15 I should strive to conserve // r16 .. r30 I can trash away // r31 reserved as an addressing temporary - but available // // extern void scaninit ( int idr, int idg, int idb, int idz ); // // extern void texinit ( int idu, int idv, int willy, int idz ); // // extern void scanline ( int *fbuffer, int *zbuffer, // int ir, int ig, int ib, int iz, int dx, // int dr, int dg, int db, int dz ); // // extern void ftexline ( int *fbuffer, int *zbuffer, // int iu, int iv, int texbase, int iz, int dx, // int idu, idv, dummy, dz ); // // extern void scansegment ( void (*fbuffer)(), // int fbuffer, int *zbuffer, // // // // FUNCTION PARAMETERS // // // DOUBLE FLOAT LOCALS // // interpolant values // we should save these first ! // // double-length float temporaries //}}} //{{{ macros //}}} .data .align 8 slope_table:: .double[16] 0 .text //{{{ scaninit ( int idr, int idg, int idb, int idz ) .globl _scaninit .align 8 _scaninit:: adds -1,r0,r31 ixfr r31, f6 addu r16 , r16 , r20 ixfr r20 , f16 addu r17 , r17 , r20 ixfr r20 , f18 addu r18 , r18 , r20 ixfr r20 , f20 addu r19 , r19 , r20 ixfr r20 , f22 fmov.ss f16 , f17 fmov.ss f18 , f19 fmov.ss f20 , f21 bri r1 fmov.ss f22 , f23 //}}} //{{{ texinit ( int idu, int idv, int compat, int idz ) .globl _texinit .align 8 _texinit:: // build f16 *2 f18 *2 f22 *2 adds -1,r0,r31 ixfr r31, f6 adds r16 , r16 , r20 and 0xffff, r20 , r20 ixfr r20 , f16 ixfr r20 , f17 adds r17 , r17 , r20 and 0xffff, r20 , r20 ixfr r20 , f18 ixfr r20 , f19 adds r19 , r19 , r20 ixfr r20 , f22 // f22 =2*idz ixfr r20 , f23 // f22 =2*idz bri r1 ixfr r18 , f20 shr 16, r18 , r20 andh 0xffff, r18 , r31 or r16,r31,r31 ixfr r31, f21 and 0xffff, r18 , r31 shl 16, r18 , r20 or r16,r31,r31 ixfr r31, f20 bri r1 nop //}}} //{{{ ascaninit ( int idr, int idg, int idb, int idz ) .text .globl _ascaninit .align 8 _ascaninit:: // ixfr r16, f8 // mov slope_table, r31 // st.l r26 ,4(r31);st.l r0, 0(r31);subs r0, r26 ,r16;st.l r16,32(r31);st.l r0,36(r31) // addu 8,r31,r31 // st.l r23 ,4(r31);st.l r0, 0(r31);subs r0, r23 ,r16;st.l r16,32(r31);st.l r0,36(r31) // addu 8,r31,r31 // st.l r24 ,4(r31);st.l r0, 0(r31);subs r0, r24 ,r16;st.l r16,32(r31);st.l r0,36(r31) // addu 8,r31,r31 // st.l r25 ,4(r31);st.l r0, 0(r31);subs r0, r25 ,r16;st.l r16,32(r31);st.l r0,36(r31) // fxfr f8 , r16 adds -1,r0,r31 ixfr r31, f6 addu r23 , r23 , r31 ixfr r31 , f16 addu r24 , r24 , r31 ixfr r31 , f18 addu r25 , r25 , r31 ixfr r31 , f20 addu r26 , r26 , r31 ixfr r31 , f22 fmov.ss f16 , f17 fmov.ss f18 , f19 fmov.ss f20 , f21 fmov.ss f22 , f23 bri r1 nop //}}} //{{{ atexinit ( int idu, int idv, int compat, int idz ) .globl _atexinit .align 8 _atexinit:: // build f16 *2 f18 *2 f22 *2 adds -1,r0,r31 ixfr r31, f6 adds r23 , r23 , r31 and 0xffff, r31 , r31 ixfr r31 , f16 ixfr r31 , f17 adds r24 , r24 , r31 and 0xffff, r31 , r31 ixfr r31 , f18 ixfr r31 , f19 adds r26 , r26 , r31 ixfr r31 , f22 // f22 =2*idz ixfr r31 , f23 // f22 =2*idz bri r1 ixfr r25 , f20 //}}} //{{{ texinit256 ( int idu, int idv, int compat, int idz ) .globl _texinit256 .align 8 _texinit256:: // build f16 *2 f18 *2 f22 *2 adds r16 , r16 , r20 ixfr r20 , f16 ixfr r20 , f17 adds r17 , r17 , r20 ixfr r20 , f18 ixfr r20 , f19 adds r19 , r19 , r20 ixfr r20 , f22 // f22 =2*idz ixfr r20 , f23 // f22 =2*idz shr 16, r18 , r20 andh 0xffff, r18 , r31 or r16,r31,r31 ixfr r31, f21 and 0xffff, r18 , r31 shl 16, r18 , r20 or r16,r31,r31 ixfr r31, f20 bri r1 nop //}}} //{{{ scanline ( int *fb, int *zb, int ir, int ig, int ib, int iz, int dx, int safeload ) .globl _scanline .align 8 // WARNING - itemp1 and itemp3 overload r18 and r19 - be careful _scanline: and 4, r16 ,r0 // if r16 &4 == 0, cc set bc .aligned // so we jump if r16 &4==0, i.e aligned .unaligned: // ie first pixel NOT on a 64-bit boundary //{{{ // r18 corresponds to high word of 64-bit pair, so we down tick to // get ir_lo etc. // // align to double boundary // addu -12, r17 , r17 fld.d 8( r17 ), f24 // load zbuffer value (from &z0-4) addu -12, r16 , r16 ixfr r18 , f9 ixfr r19 , f11 ixfr r20 , f13 ixfr r21 , f15 // construct lo word of rgbz by subtraction subu r18 , r23 , r31 ixfr r31, f8 subu r19 , r24 , r31 ixfr r31, f10 subu r20 , r25 , r31 ixfr r31, f12 subu r21 , r26 , r31 adds -1,r0, r18 fmov.ss f6 , f14 // important - zlo MUST be invisible for fchkz adds 1, r22 , r22 // tick count fzchkl f24 , f14 , f26 // f14 -check with frigged f14 ixfr r31, f14 // correct f14 br .aligned_path and 1, r22 , r19 // r19 = extras on rhs //}}} .aligned: // ie first pixel IS on a 64-bit boundary //{{{ // // write r21 into dbl f14 lo, r21 + f22 into dbl f14 hi etc // addu -8, r17 , r17 fld.d 8( r17 ), f24 // load zbuffer value HOURS to complete addu -8, r16 , r16 ixfr r18 , f8 ixfr r19 , f10 ixfr r20 , f12 ixfr r21 , f14 addu r20 , r25 , r31 ixfr r31, f13 addu r19 , r24 , r31 ixfr r31, f11 addu r18 , r23 , r31 ixfr r31, f9 addu r21 , r26 , r31 ixfr r31, f15 adds -1,r0, r18 .dual fzchkl f24 , f14 , f26 // f14 -check with unfrigged f14 and 1, r22 , r19 // r19 = extras on rhs .aligned_path: faddp f12 ,f0,f0 or r0, r22 ,r31 // r31 = orig r22 faddp f10 ,f0,f0 shr 1, r22 , r22 // r22 now n of 2s faddp f8 ,f0,f0 adds -2, r31, r0 // goto last 4 if r22 < 2 form f0, f28 bc .last_few fnop adds -1, r22 , r22 // corrected for autoincrement, so test -3 below fnop bla r18 , r22 , .inner_loop //}}} //{{{ 32-bit f14 , 32-bit pixel inner loop OPENED out in 2s .inner_loop_db: fzchks f0,f0,f0 nop .inner_loop: fzchkl f0,f0,f0 fst.d f26 , 8( r17 )++ faddz f14 , f22 , f14 nop faddp f12 , f20 , f12 pst.d f28 , 8( r16 )++ faddp f10 , f18 , f10 nop faddp f8 , f16 , f8 fld.d 8( r17 ), f24 form f0, f28 bla r18 , r22 ,.inner_loop_db fzchkl f24 , f14 , f26 or r0, r19 ,r0 // for exit condition code form f0,f0 bc .zb_exit //}}} //{{{ there is just 1 pixel to go // // this is fortunate - if pixels left = 1, then we CANT have a -1 // mask in f14 , since it would have bumped r22 to 2 // // we only enter here if pixels == 1 and that pixel is on screen // so we unconditionally mask off hi word, re-execute the fzchkl // and proceed // .last_few: fmov.ss f6 , f15 nop fzchkl f24 , f14 , f26 nop fzchks f0,f0,f0 // trash 4 PM bits fst.d f26 , 8( r17 )++ .enddual fzchkl f0,f0,f0 // and 2 more PM bits bri r1 fnop pst.d f28 , 8( r16 )++ .zb_exit:: fnop bri r1 fnop nop //}}} //}}} //{{{ flatline ( int *fb, int *zb, int ir, int ig, int ib, int iz, int dx, int safeload ) .globl _flatline .align 8 // WARNING - itemp1 and itemp3 overload r18 and r19 - be careful _flatline: ixfr r18 , f9 ixfr r19 , f11 ixfr r20 , f13 fmov.ss f9 , f8 fmov.ss f11 , f10 fmov.ss f13 , f12 and 4, r16 ,r0 // if r16 &4 == 0, cc set bc .faligned // so we jump if r16 &4==0, i.e aligned .funaligned: // ie first pixel NOT on a 64-bit boundary //{{{ // r18 corresponds to high word of 64-bit pair, so we down tick to // get ir_lo etc. // // align to double boundary // addu -12, r17 , r17 addu -12, r16 , r16 fld.d 8( r17 ), f24 // load zbuffer value (from &z0-4) ixfr r21 , f15 // construct lo word of rgbz by subtraction subu r21 , r26 , r31 adds -1,r0, r18 fmov.ss f6 , f14 // important - zlo MUST be invisible for fchkz adds 1, r22 , r22 // tick count fzchkl f24 , f14 , f26 // f14 -check with frigged f14 ixfr r31, f14 // correct f14 br .faligned_path and 1, r22 , r19 // r19 = extras on rhs //}}} .faligned: // ie first pixel IS on a 64-bit boundary //{{{ // // write r21 into dbl f14 lo, r21 + f22 into dbl f14 hi etc // addu -8, r17 , r17 addu -8, r16 , r16 fld.d 8( r17 ), f24 // load zbuffer value HOURS to complete ixfr r21 , f14 addu r21 , r26 , r31 ixfr r31, f15 // this needs 3 cycles to complete before fzchkl adds -1,r0, r18 .dual fzchkl f24 , f14 , f26 // f14 -check with unfrigged f14 and 1, r22 , r19 // r19 = extras on rhs .faligned_path: faddp f12 ,f0,f0 or r0, r22 ,r31 // r31 = orig r22 faddp f10 ,f0,f0 shr 1, r22 , r22 // r22 now n of 4s faddp f8 ,f0,f0 adds -2, r31, r0 // goto last 4 if r22 < 2 form f0, f28 bc .flast_few fnop adds -1, r22 , r22 // corrected for autoincrement, so test -3 below fnop bla r18 , r22 , .finner_loop //}}} //{{{ 32-bit f14 , 32-bit flat shaded pixel inner loop OPENED out in 2s .finner_loop_db: fzchks f0,f0,f0 fst.d f26 , 8( r17 )++ .finner_loop: fzchkl f0,f0,f0 fld.d 8( r17 ), f24 faddz f14 , f22 , f14 pst.d f28 , 8( r16 )++ fnop bla r18 , r22 ,.finner_loop_db fzchkl f24 , f14 , f26 or r0, r19 ,r0 // for exit condition code // weve exited the loop here form f0,f0 bc .fzb_exit //}}} //{{{ there is just 1 pixel to go // // this is fortunate - if pixels left = 1, then we CANT have a -1 // mask in f14 , since it would have bumped r22 to 2 // // we only enter here if pixels == 1 and that pixel is on screen // so we unconditionally mask off hi word, re-execute the fzchkl // and proceed // .flast_few: fmov.ss f6 , f15 nop pfzchkl f24 , f14 ,f0 // f26 nop pfzchks f0,f0, f26 // trash 4 PM bits fst.d f26 , 8( r17 )++ .enddual pfzchkl f0,f0,f0 // and 2 more PM bits bri r1 fnop pst.d f28 , 8( r16 )++ .fzb_exit: fnop bri r1 fnop nop //}}} //}}} //{{{ ftexline ( *fb, *zb, f8 , f10 , *tb, f14 , dx, f16 , f18 , DUMMY , f22 ) .globl _ftexline .align 8 // WARNING - r18 and r19 overload ir and ig - be careful _ftexline:: fxfr f20 , r20 and 4, r16 ,r0 // if r16 &7 == 0, cc set bc .txaligned // so we jump if r16 &7==0, i.e aligned .txunaligned: // ie first pixel NOT on a 64-bit boundary //{{{ // align to double boundary adds -12, r17 , r17 adds -12, r16 , r16 fld.d 8( r17 ), f24 // load zbuffer value (from &z0-4) // correct for interpolant over-tick - first f8 , f10 subs r18 , r23 , r31 and 0xffff,r31,r31 ixfr r31, f8 and 0xffff, r18 ,r31 ixfr r31, f9 subs r19 , r24 , r31 and 0xffff,r31,r31 ixfr r31, f10 and 0xffff, r19 ,r31 ixfr r31, f11 ixfr r21 , f15 adds -1,r0, r25 fmov.ss f6 , f14 // important - zlo MUST be invisible for fchkz adds 1, r22 , r22 // tick count fzchkl f24 , f14 , f26 // f14 -check with frigged f14 subs r21 , r26 , r31 and 1, r22 , r18 // r18 = extras on rhs br .txaligned_path ixfr r31, f14 // correct f14 //}}} .txaligned: // ie first pixel IS on a 64-bit boundary //{{{ // // write r21 into dbl f14 lo, r21 + f22 into dbl f14 hi etc // adds -8, r17 , r17 adds -8, r16 , r16 fld.d 8( r17 ), f24 // load zbuffer value HOURS to complete ixfr r21 , f14 adds r21 , r26 , r31 ixfr r31, f15 // this needs 3 cycles to complete before fzchkl and 0xffff, r18 ,r31 ixfr r31, f8 addu r18 , r23 , r31 and 0xffff,r31,r31 ixfr r31, f9 and 0xffff, r19 ,r31 ixfr r31, f10 addu r19 , r24 , r31 and 0xffff,r31,r31 ixfr r31, f11 adds -1,r0, r25 .dual fzchkl f24 , f14 , f26 // f14 -check with unfrigged f14 and 1, r22 , r18 // r18 = extras on rhs //}}} .txaligned_path: // above branches re-merge here //{{{ form f0,f0 // clear merge to start up or r0, r22 ,r31 // r31 = orig r22 faddp f8 ,f0,f0 shr 1, r22 , r22 // r22 now n of 2s faddp f10 ,f0,f0 adds -2, r31, r0 // goto last few if r22 < 2 form f0, f28 bc .txlast_few fnop adds -1, r22 , r22 // corrected for autoincrement, so test -3 below fnop bla r25 , r22 , .txinner_loop //}}} //{{{ 32-bit f14 , texture inner loop, 2 pixels at a time .txinner_loop_db: fxfr f28 ,r31 // r31 = low pixel interpolated f8 , f10 fst.d f26 , 8( r17 ) // IMPORTANT - we cannot auto-increment .txinner_loop: fxfr f29 , r19 // in same cycle as fxfr ! ! ! ! ! fld.d 16( r17 ), f24 faddz f14 , f22 , f14 shr 2,r31,r31 // drop 2 of 4 blue bits, i.e word address fzchks f0,f0,f0 // drop 4 more PM bits shr 2, r19 , r19 fzchkl f0,f0,f0 // drop 2 more PM bits fld.l r20 (r31), f30 faddp f8 , f16 , f8 fld.l r20 ( r19 ), f31 faddp f10 , f18 , f10 addu 8, r17 , r17 // see note on r17 ++ above fnop ld.c psr,r31 // r31 holds 16-bit pixel size form f0, f28 // and merge the colour ready for next xorh 0x00c0,r31, r19 // 0xc flips 32-16 fnop // r19 holds 32-bit pixelsize st.c r19 , psr // goto 32 bits fnop pst.d f30 , 8( r16 )++ // do pixel store fnop st.c r31, psr // and go back to 16 bits fnop bla r25 , r22 ,.txinner_loop_db fzchkl f24 , f14 , f26 nop // weve exited the loop here fnop or r0, r18 ,r0 fnop bc .tx_exit //}}} //{{{ there is just 1 pixel to go - we have a good f14 in f26 , and 2 good cols .txlast_few: // we CANNOT ixfr and fxfr fmov.ss f6 , f15 nop fxfr f28 ,r31 // txtemp1 = interpolated f8 , f10 nop fzchkl f24 , f14 , f26 shr 2,r31,r31 fzchks f0,f0,f0 // trash 4 PM bits fld.l r20 (r31), f28 fzchkl f0,f0,f0 // and 2 more PM bits fst.d f26 , 8( r17 )++ fnop ld.c psr,r31 fnop xorh 0x00c0,r31, r19 fnop st.c r19 , psr fnop pst.d f28 , 8( r16 )++ fnop st.c r31,psr .tx_exit: .enddual form f0,f0 bri r1 form f0,f0 nop //}}} //}}} //{{{ ftexline256 ( *fb, *zb, f8 , f10 , *tb, f14 , dx, f16 , f18 , DUMMY , f22 ) .globl _ftexline256 .align 8 // WARNING - r18 and r19 overload ir and ig - be careful _ftexline256:: fxfr f20 , r20 and 4, r16 ,r0 // if r16 &7 == 0, cc set bc .txaligned256 // so we jump if r16 &7==0, i.e aligned .txunaligned256: // ie first pixel NOT on a 64-bit boundary //{{{ // align to double boundary adds -12, r17 , r17 adds -12, r16 , r16 fld.d 8( r17 ), f24 // load zbuffer value (from &z0-4) // correct for interpolant over-tick - first f8 , f10 subs r18 , r23 , r31 and 0xffff,r31,r31 ixfr r31, f8 and 0xffff, r18 ,r31 ixfr r31, f9 subs r19 , r24 , r31 and 0xffff,r31,r31 ixfr r31, f10 and 0xffff, r19 ,r31 ixfr r31, f11 ixfr r21 , f15 adds -1,r0, r25 fmov.ss f6 , f14 // important - zlo MUST be invisible for fchkz adds 1, r22 , r22 // tick count fzchkl f24 , f14 , f26 // f14 -check with frigged f14 subs r21 , r26 , r31 and 1, r22 , r18 // r18 = extras on rhs br .txaligned_path256 ixfr r31, f14 // correct f14 //}}} .txaligned256: // ie first pixel IS on a 64-bit boundary //{{{ // // write r21 into dbl f14 lo, r21 + f22 into dbl f14 hi etc // adds -8, r17 , r17 adds -8, r16 , r16 fld.d 8( r17 ), f24 // load zbuffer value HOURS to complete ixfr r21 , f14 adds r21 , r26 , r31 ixfr r31, f15 // this needs 3 cycles to complete before fzchkl ixfr r18 , f8 addu r18 , r23 , r31 ixfr r31, f9 ixfr r19 , f10 addu r19 , r24 , r31 ixfr r31, f11 adds -1,r0, r25 .dual fzchkl f24 , f14 , f26 // f14 -check with unfrigged f14 and 1, r22 , r18 // r18 = extras on rhs //}}} .txaligned_path256: // above branches re-merge here //{{{ form f0,f0 // clear merge to start up or r0, r22 ,r31 // r31 = orig r22 faddp f8 ,f0,f0 shr 1, r22 , r22 // r22 now n of 2s faddp f10 ,f0,f0 adds -2, r31, r0 // goto last few if r22 < 2 form f0, f28 bc .txlast_few256 fnop adds -1, r22 , r22 // corrected for autoincrement, so test -3 below fnop bla r25 , r22 , .txinner_loop256 //}}} //{{{ 32-bit f14 , texture inner loop, 2 pixels at a time .txinner_loop_db256: fxfr f28 ,r31 // r31 = low pixel interpolated f8 , f10 fst.d f26 , 8( r17 ) // IMPORTANT - we cannot auto-increment .txinner_loop256: fxfr f29 , r19 // in same cycle as fxfr ! ! ! ! ! fld.d 16( r17 ), f24 faddz f14 , f22 , f14 shr 6,r31,r31 // drop 6 of 8 blue bits, i.e word address fzchks f0,f0,f0 // drop 4 more PM bits shr 6, r19 , r19 fzchkl f0,f0,f0 // drop 2 more PM bits fld.l r20 (r31), f30 faddp f8 , f16 , f8 fld.l r20 ( r19 ), f31 faddp f10 , f18 , f10 addu 8, r17 , r17 // see note on r17 ++ above form f0, f28 // and merge the colour ready for next pst.d f30 , 8( r16 )++ // do pixel store fnop bla r25 , r22 ,.txinner_loop_db256 fzchkl f24 , f14 , f26 nop // weve exited the loop here fnop or r0, r18 ,r0 fnop bc .tx_exit256 //}}} //{{{ there is just 1 pixel to go - we have a good f14 in f26 , and 2 good cols .txlast_few256: // we CANNOT ixfr and fxfr fmov.ss f6 , f15 nop fxfr f28 ,r31 // txtemp1 = interpolated f8 , f10 nop fzchkl f24 , f14 , f26 shr 6,r31,r31 fzchks f0,f0,f0 // trash 4 PM bits fld.l r20 (r31), f28 fzchkl f0,f0,f0 // and 2 more PM bits fst.d f26 , 8( r17 )++ fnop pst.d f28 , 8( r16 )++ .tx_exit256: .enddual form f0,f0 bri r1 form f0,f0 nop //}}} //}}} //{{{ 32-bit f14 , 32-bit pixel inner loop OPENED out in 4s // .inner4_loop: // pfaddz f14 , f22 ,f0 // fld.d 16(zaddr), dbltemp // pfzchkl dbltemp, f14 , f14 // nop // pfaddz f14 , f22 ,dbltemp // fst.d f26 , 8(zaddr) // pfzchkl f0,f0, f14 // now 4 pixels worth of mask is ready // nop // faddp f12 , f20 , f12 // fst.d dbltemp, 16(zaddr)++ // faddp f10 , f18 , f10 // nop // faddp f8 , f16 , f8 // pst.d f28 , 8(paddr)++ // form f0, f28 // nop // faddp f12 , f20 , f12 // nop // adds -4, dx, dx // faddp f10 , f18 , f10 // pst.d f28 , 8(paddr)++ // faddp f8 , f16 , f8 // nop // form f0, f28 // bla minus1,dx,.inner4_loop // bnc.t .inner4_loop // fzchkl f24 , f14 , f26 // nop // // weve exited the loop here // fnop // or r0,itemp3,r0 // for exit condition code // fnop // bc .zb_exit //}}} //{{{ 32-bit f14 , flat pixel inner loop OPENED out in 4s // .flat4_loop: // pfaddz f14 , f22 ,f0 // fld.d 16(zaddr), dbltemp // pfzchkl dbltemp, f14 , f14 // fst.d f26 , 8(zaddr) // pfaddz f14 , f22 ,dbltemp // nop // pfzchkl f0,f0, f14 // now 4 pixels worth of mask is ready // fst.d dbltemp, 16(zaddr)++ // fnop // pst.d f28 , 8(paddr)++ // fnop // pst.d f28 , 8(paddr)++ // fnop // bla minus1,dx,.flat4_loop // fzchkl f24 , f14 , f26 // nop // // weve exited the loop here // fnop // or r0,itemp3,r0 // for exit condition code // fnop // bc .zb_exit //}}} //{{{ setpixelsize // // Set pixel width - 00 == 8 bits // 01 == 16 // 10 == 32 // // PSRMASK = 0x00c0 .globl _setpixelsize _setpixelsize:: ld.c psr,r31 andnoth PSRMASK,r31,r31 shl 22,r16,r16 or r16,r31,r31 st.c r31,psr bri r1 or r31, r0, r16 //}}} //{{{ getpixelsize // // Set pixel width - 00 == 8 bits // 01 == 16 // 10 == 32 // // PSRMASKALL = 0x00c0 .globl _getpixelsize _getpixelsize:: ld.c psr,r31 andh PSRMASKALL,r31,r31 bri r1 shr 22,r31,r16 //}}} //{{{ setdirectmode .globl _setdirectmode _setdirectmode:: ld.c dirbase,r31 and -2,r31,r31 st.c r31,dirbase bri r1 nop //}}} //{{{ clear store // // Clear Store // // assumes .quad aligned data // .globl _clear_store _clear_store:: ixfr r17,f16 ixfr r17,f17 ixfr r17,f18 ixfr r17,f19 adds -16,r18,r18 adds -16,r0,r19 // loop increment bla r19,r18,init_loop addu -16,r16,r16 // adjust address for autoincrement init_loop: bla r19,r18,init_loop fst.q f16,16(r16)++ bri r1 nop //}}} //{{{ thrash // // thrash // // // thrash (loation, times) // // .globl _thrash _thrash:: adds -1, r0, r18 ixfr r18,f8 bla r18,r17,thrash_loop nop thrash_loop: fld.l r0(r16),f8 bla r18,r17,thrash_loop fst.l f8,r0(r16) bri r1 nop //}}} // this is the end .data