CydandClaude Opus 4.8
4b6d910f7b
- vpxlog.cpp: VPX_FIFODUMP=<path> records every FIFO burst ('VPXM' records)
- decode_fifodump.py: action census + payload dumps of a capture
- render_capture.py: reconstruct the DPL scene graph from a capture and
software-render each draw_scene frame (camera, view, materials, geometry
all taken from the wire)
- divrgb.conf + divrgb.fifodump: flyk divrgb.scn capture fixture
- divrgb-decoded.png / divrgb-frame0.png: first images ever produced from
the Rel 4.10 VPX protocol without a real board -- the textbook SMPTE
color-bar pattern, validating verts/conns/materials/camera in one shot
- PHASE3-PROGRESS.md: the established Rel 4.10 wire protocol (action map,
node types, message layouts); RENDER-HARNESS.md updated
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
25 lines
466 B
Plaintext
25 lines
466 B
Plaintext
[sdl]
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output=opengl
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[dosbox]
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memsize=32
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machine=svga_s3
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[cpu]
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core=normal
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cputype=pentium
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cycles=20000
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[serial]
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serial1=disabled
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serial2=disabled
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[autoexec]
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mount c "C:\VWE\TeslaRel410\ALPHA_1"
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c:
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cd \VWETEST\VGLTEST
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set VIDEOFORMAT=svga
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set TEMP=c:\
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set DPLARG=/tranny~division\vrendmon.btl~/i860~division\vrend.mng~/device~0x150~/video~svga~/pipes~1~/qual~0x14
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32rtm.exe -x
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flyk.exe divrgb.scn ..\cycle\camera.spl
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32rtm.exe -u
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echo FLYK-DONE rc=%errorlevel%
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pause
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