CydandClaude Fable 5
db7745fcd0
Un-ignored: the dev drive is the ground truth the restoration and emulator work constantly reference (DPL3/LIBDPL + VRENDER i860 renderer source, BT/RP live+dev game trees, VGL_LABS pod boot, scene/audio content). Kept in-repo for the pod-owner community. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
1263 lines
28 KiB
ArmAsm
1263 lines
28 KiB
ArmAsm
// nicked from output of PGC Rel 1.4 -opt 2
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.text
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.align 8
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.text
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//{{{ register allocation
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//
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// r1 return address
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// r2 sp
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// r3 frameP
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// r4 .. r15 I should strive to conserve
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// r16 .. r30 I can trash away
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// r31 reserved as an addressing temporary - but available
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//
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// extern void scaninit ( int idr, int idg, int idb, int idz );
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//
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// extern void texinit ( int idu, int idv, int willy, int idz );
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//
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// extern void scanline ( int *fbuffer, int *zbuffer,
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// int ir, int ig, int ib, int iz, int dx,
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// int dr, int dg, int db, int dz );
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//
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// extern void ftexline ( int *fbuffer, int *zbuffer,
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// int iu, int iv, int texbase, int iz, int dx,
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// int idu, idv, dummy, dz );
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//
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// extern void scansegment ( void (*fbuffer)(),
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// int fbuffer, int *zbuffer,
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//
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//
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//
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// FUNCTION PARAMETERS
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//
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//
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// DOUBLE FLOAT LOCALS
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//
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// interpolant values
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// we should save these first !
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//
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// double-length float temporaries
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//}}}
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//{{{ macros
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//}}}
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.data
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.align 8
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slope_table::
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.double[16] 0
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.text
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//{{{ scaninit ( int idr, int idg, int idb, int idz )
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.globl _scaninit
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.align 8
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_scaninit::
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adds -1,r0,r31
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ixfr r31, f6
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addu r16 , r16 , r20
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ixfr r20 , f16
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addu r17 , r17 , r20
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ixfr r20 , f18
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addu r18 , r18 , r20
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ixfr r20 , f20
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addu r19 , r19 , r20
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ixfr r20 , f22
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fmov.ss f16 , f17
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fmov.ss f18 , f19
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fmov.ss f20 , f21
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bri r1
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fmov.ss f22 , f23
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//}}}
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//{{{ texinit ( int idu, int idv, int compat, int idz )
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.globl _texinit
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.align 8
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_texinit::
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// build f16 *2 f18 *2 f22 *2
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adds -1,r0,r31
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ixfr r31, f6
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adds r16 , r16 , r20
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and 0xffff, r20 , r20
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ixfr r20 , f16
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ixfr r20 , f17
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adds r17 , r17 , r20
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and 0xffff, r20 , r20
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ixfr r20 , f18
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ixfr r20 , f19
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adds r19 , r19 , r20
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ixfr r20 , f22 // f22 =2*idz
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ixfr r20 , f23 // f22 =2*idz
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bri r1
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ixfr r18 , f20
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shr 16, r18 , r20
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andh 0xffff, r18 , r31
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or r16,r31,r31
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ixfr r31, f21
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and 0xffff, r18 , r31
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shl 16, r18 , r20
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or r16,r31,r31
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ixfr r31, f20
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bri r1
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nop
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//}}}
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//{{{ ascaninit ( int idr, int idg, int idb, int idz )
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.text
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.globl _ascaninit
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.align 8
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_ascaninit::
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// ixfr r16, f8
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// mov slope_table, r31
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// st.l r26 ,4(r31);st.l r0, 0(r31);subs r0, r26 ,r16;st.l r16,32(r31);st.l r0,36(r31)
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// addu 8,r31,r31
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// st.l r23 ,4(r31);st.l r0, 0(r31);subs r0, r23 ,r16;st.l r16,32(r31);st.l r0,36(r31)
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// addu 8,r31,r31
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// st.l r24 ,4(r31);st.l r0, 0(r31);subs r0, r24 ,r16;st.l r16,32(r31);st.l r0,36(r31)
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// addu 8,r31,r31
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// st.l r25 ,4(r31);st.l r0, 0(r31);subs r0, r25 ,r16;st.l r16,32(r31);st.l r0,36(r31)
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// fxfr f8 , r16
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adds -1,r0,r31
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ixfr r31, f6
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addu r23 , r23 , r31
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ixfr r31 , f16
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addu r24 , r24 , r31
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ixfr r31 , f18
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addu r25 , r25 , r31
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ixfr r31 , f20
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addu r26 , r26 , r31
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ixfr r31 , f22
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fmov.ss f16 , f17
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fmov.ss f18 , f19
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fmov.ss f20 , f21
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fmov.ss f22 , f23
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bri r1
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nop
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//}}}
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//{{{ atexinit ( int idu, int idv, int compat, int idz )
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.globl _atexinit
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.align 8
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_atexinit::
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// build f16 *2 f18 *2 f22 *2
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adds -1,r0,r31
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ixfr r31, f6
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adds r23 , r23 , r31
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and 0xffff, r31 , r31
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ixfr r31 , f16
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ixfr r31 , f17
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adds r24 , r24 , r31
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and 0xffff, r31 , r31
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ixfr r31 , f18
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ixfr r31 , f19
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adds r26 , r26 , r31
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ixfr r31 , f22 // f22 =2*idz
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ixfr r31 , f23 // f22 =2*idz
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bri r1
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ixfr r25 , f20
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//}}}
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//{{{ texinit256 ( int idu, int idv, int compat, int idz )
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.globl _texinit256
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.align 8
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_texinit256::
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// build f16 *2 f18 *2 f22 *2
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adds r16 , r16 , r20
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ixfr r20 , f16
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ixfr r20 , f17
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adds r17 , r17 , r20
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ixfr r20 , f18
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ixfr r20 , f19
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adds r19 , r19 , r20
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ixfr r20 , f22 // f22 =2*idz
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ixfr r20 , f23 // f22 =2*idz
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shr 16, r18 , r20
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andh 0xffff, r18 , r31
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or r16,r31,r31
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ixfr r31, f21
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and 0xffff, r18 , r31
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shl 16, r18 , r20
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or r16,r31,r31
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ixfr r31, f20
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bri r1
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nop
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//}}}
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//{{{ scanline ( int *fb, int *zb, int ir, int ig, int ib, int iz, int dx, int safeload )
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.globl _scanline
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.align 8
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// WARNING - itemp1 and itemp3 overload r18 and r19 - be careful
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_scanline:
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and 4, r16 ,r0 // if r16 &4 == 0, cc set
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bc .aligned // so we jump if r16 &4==0, i.e aligned
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.unaligned: // ie first pixel NOT on a 64-bit boundary
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//{{{
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// r18 corresponds to high word of 64-bit pair, so we down tick to
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// get ir_lo etc.
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//
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// align to double boundary
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//
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addu -12, r17 , r17
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fld.d 8( r17 ), f24 // load zbuffer value (from &z0-4)
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addu -12, r16 , r16
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ixfr r18 , f9
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ixfr r19 , f11
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ixfr r20 , f13
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ixfr r21 , f15
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// construct lo word of rgbz by subtraction
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subu r18 , r23 , r31
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ixfr r31, f8
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subu r19 , r24 , r31
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ixfr r31, f10
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subu r20 , r25 , r31
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ixfr r31, f12
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subu r21 , r26 , r31
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adds -1,r0, r18
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fmov.ss f6 , f14 // important - zlo MUST be invisible for fchkz
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adds 1, r22 , r22 // tick count
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fzchkl f24 , f14 , f26 // f14 -check with frigged f14
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ixfr r31, f14 // correct f14
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br .aligned_path
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and 1, r22 , r19 // r19 = extras on rhs
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//}}}
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.aligned: // ie first pixel IS on a 64-bit boundary
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//{{{
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//
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// write r21 into dbl f14 lo, r21 + f22 into dbl f14 hi etc
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//
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addu -8, r17 , r17
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fld.d 8( r17 ), f24 // load zbuffer value HOURS to complete
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addu -8, r16 , r16
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ixfr r18 , f8
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ixfr r19 , f10
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ixfr r20 , f12
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ixfr r21 , f14
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addu r20 , r25 , r31
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ixfr r31, f13
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addu r19 , r24 , r31
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ixfr r31, f11
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addu r18 , r23 , r31
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ixfr r31, f9
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addu r21 , r26 , r31
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ixfr r31, f15
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adds -1,r0, r18
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.dual
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fzchkl f24 , f14 , f26 // f14 -check with unfrigged f14
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and 1, r22 , r19 // r19 = extras on rhs
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.aligned_path:
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faddp f12 ,f0,f0
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or r0, r22 ,r31 // r31 = orig r22
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faddp f10 ,f0,f0
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shr 1, r22 , r22 // r22 now n of 2s
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faddp f8 ,f0,f0
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adds -2, r31, r0 // goto last 4 if r22 < 2
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form f0, f28
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bc .last_few
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fnop
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adds -1, r22 , r22 // corrected for autoincrement, so test -3 below
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fnop
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bla r18 , r22 , .inner_loop
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//}}}
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//{{{ 32-bit f14 , 32-bit pixel inner loop OPENED out in 2s
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.inner_loop_db:
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fzchks f0,f0,f0
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nop
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.inner_loop:
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fzchkl f0,f0,f0
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fst.d f26 , 8( r17 )++
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faddz f14 , f22 , f14
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nop
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faddp f12 , f20 , f12
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pst.d f28 , 8( r16 )++
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faddp f10 , f18 , f10
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nop
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faddp f8 , f16 , f8
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fld.d 8( r17 ), f24
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form f0, f28
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bla r18 , r22 ,.inner_loop_db
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fzchkl f24 , f14 , f26
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or r0, r19 ,r0 // for exit condition code
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form f0,f0
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bc .zb_exit
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//}}}
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//{{{ there is just 1 pixel to go
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//
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// this is fortunate - if pixels left = 1, then we CANT have a -1
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// mask in f14 , since it would have bumped r22 to 2
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//
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// we only enter here if pixels == 1 and that pixel is on screen
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// so we unconditionally mask off hi word, re-execute the fzchkl
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// and proceed
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//
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.last_few:
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fmov.ss f6 , f15
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nop
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fzchkl f24 , f14 , f26
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nop
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fzchks f0,f0,f0 // trash 4 PM bits
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fst.d f26 , 8( r17 )++
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.enddual
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fzchkl f0,f0,f0 // and 2 more PM bits
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bri r1
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fnop
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pst.d f28 , 8( r16 )++
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.zb_exit::
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fnop
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bri r1
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fnop
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nop
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//}}}
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//}}}
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//{{{ flatline ( int *fb, int *zb, int ir, int ig, int ib, int iz, int dx, int safeload )
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.globl _flatline
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.align 8
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// WARNING - itemp1 and itemp3 overload r18 and r19 - be careful
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_flatline:
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ixfr r18 , f9
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ixfr r19 , f11
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ixfr r20 , f13
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fmov.ss f9 , f8
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fmov.ss f11 , f10
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fmov.ss f13 , f12
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and 4, r16 ,r0 // if r16 &4 == 0, cc set
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bc .faligned // so we jump if r16 &4==0, i.e aligned
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.funaligned: // ie first pixel NOT on a 64-bit boundary
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//{{{
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// r18 corresponds to high word of 64-bit pair, so we down tick to
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// get ir_lo etc.
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//
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// align to double boundary
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//
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addu -12, r17 , r17
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addu -12, r16 , r16
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fld.d 8( r17 ), f24 // load zbuffer value (from &z0-4)
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ixfr r21 , f15
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// construct lo word of rgbz by subtraction
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subu r21 , r26 , r31
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adds -1,r0, r18
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fmov.ss f6 , f14 // important - zlo MUST be invisible for fchkz
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adds 1, r22 , r22 // tick count
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fzchkl f24 , f14 , f26 // f14 -check with frigged f14
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ixfr r31, f14 // correct f14
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br .faligned_path
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and 1, r22 , r19 // r19 = extras on rhs
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//}}}
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.faligned: // ie first pixel IS on a 64-bit boundary
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//{{{
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//
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// write r21 into dbl f14 lo, r21 + f22 into dbl f14 hi etc
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//
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addu -8, r17 , r17
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addu -8, r16 , r16
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fld.d 8( r17 ), f24 // load zbuffer value HOURS to complete
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ixfr r21 , f14
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addu r21 , r26 , r31
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ixfr r31, f15 // this needs 3 cycles to complete before fzchkl
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adds -1,r0, r18
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.dual
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fzchkl f24 , f14 , f26 // f14 -check with unfrigged f14
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and 1, r22 , r19 // r19 = extras on rhs
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.faligned_path:
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faddp f12 ,f0,f0
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or r0, r22 ,r31 // r31 = orig r22
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faddp f10 ,f0,f0
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shr 1, r22 , r22 // r22 now n of 4s
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faddp f8 ,f0,f0
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adds -2, r31, r0 // goto last 4 if r22 < 2
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form f0, f28
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bc .flast_few
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fnop
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adds -1, r22 , r22 // corrected for autoincrement, so test -3 below
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fnop
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bla r18 , r22 , .finner_loop
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//}}}
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//{{{ 32-bit f14 , 32-bit flat shaded pixel inner loop OPENED out in 2s
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.finner_loop_db:
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fzchks f0,f0,f0
|
|
fst.d f26 , 8( r17 )++
|
|
.finner_loop:
|
|
fzchkl f0,f0,f0
|
|
fld.d 8( r17 ), f24
|
|
faddz f14 , f22 , f14
|
|
pst.d f28 , 8( r16 )++
|
|
fnop
|
|
bla r18 , r22 ,.finner_loop_db
|
|
fzchkl f24 , f14 , f26
|
|
or r0, r19 ,r0 // for exit condition code
|
|
// weve exited the loop here
|
|
form f0,f0
|
|
bc .fzb_exit
|
|
//}}}
|
|
|
|
//{{{ there is just 1 pixel to go
|
|
//
|
|
// this is fortunate - if pixels left = 1, then we CANT have a -1
|
|
// mask in f14 , since it would have bumped r22 to 2
|
|
//
|
|
// we only enter here if pixels == 1 and that pixel is on screen
|
|
// so we unconditionally mask off hi word, re-execute the fzchkl
|
|
// and proceed
|
|
//
|
|
|
|
.flast_few:
|
|
fmov.ss f6 , f15
|
|
nop
|
|
pfzchkl f24 , f14 ,f0 // f26
|
|
nop
|
|
pfzchks f0,f0, f26 // trash 4 PM bits
|
|
fst.d f26 , 8( r17 )++
|
|
.enddual
|
|
pfzchkl f0,f0,f0 // and 2 more PM bits
|
|
bri r1
|
|
fnop
|
|
pst.d f28 , 8( r16 )++
|
|
.fzb_exit:
|
|
fnop
|
|
bri r1
|
|
fnop
|
|
nop
|
|
//}}}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//}}}
|
|
//{{{ ftexline ( *fb, *zb, f8 , f10 , *tb, f14 , dx, f16 , f18 , DUMMY , f22 )
|
|
.globl _ftexline
|
|
.align 8
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// WARNING - r18 and r19 overload ir and ig - be careful
|
|
|
|
_ftexline::
|
|
|
|
fxfr f20 , r20
|
|
and 4, r16 ,r0 // if r16 &7 == 0, cc set
|
|
bc .txaligned // so we jump if r16 &7==0, i.e aligned
|
|
|
|
.txunaligned: // ie first pixel NOT on a 64-bit boundary
|
|
//{{{
|
|
// align to double boundary
|
|
|
|
adds -12, r17 , r17
|
|
adds -12, r16 , r16
|
|
|
|
fld.d 8( r17 ), f24 // load zbuffer value (from &z0-4)
|
|
|
|
// correct for interpolant over-tick - first f8 , f10
|
|
|
|
subs r18 , r23 , r31
|
|
and 0xffff,r31,r31
|
|
ixfr r31, f8
|
|
|
|
and 0xffff, r18 ,r31
|
|
ixfr r31, f9
|
|
|
|
subs r19 , r24 , r31
|
|
and 0xffff,r31,r31
|
|
ixfr r31, f10
|
|
|
|
and 0xffff, r19 ,r31
|
|
ixfr r31, f11
|
|
|
|
ixfr r21 , f15
|
|
|
|
adds -1,r0, r25
|
|
fmov.ss f6 , f14 // important - zlo MUST be invisible for fchkz
|
|
|
|
adds 1, r22 , r22 // tick count
|
|
|
|
fzchkl f24 , f14 , f26 // f14 -check with frigged f14
|
|
subs r21 , r26 , r31
|
|
and 1, r22 , r18 // r18 = extras on rhs
|
|
br .txaligned_path
|
|
ixfr r31, f14 // correct f14
|
|
//}}}
|
|
.txaligned: // ie first pixel IS on a 64-bit boundary
|
|
//{{{
|
|
//
|
|
// write r21 into dbl f14 lo, r21 + f22 into dbl f14 hi etc
|
|
//
|
|
adds -8, r17 , r17
|
|
adds -8, r16 , r16
|
|
|
|
fld.d 8( r17 ), f24 // load zbuffer value HOURS to complete
|
|
|
|
ixfr r21 , f14
|
|
adds r21 , r26 , r31
|
|
ixfr r31, f15 // this needs 3 cycles to complete before fzchkl
|
|
|
|
and 0xffff, r18 ,r31
|
|
ixfr r31, f8
|
|
addu r18 , r23 , r31
|
|
and 0xffff,r31,r31
|
|
ixfr r31, f9
|
|
|
|
and 0xffff, r19 ,r31
|
|
ixfr r31, f10
|
|
addu r19 , r24 , r31
|
|
and 0xffff,r31,r31
|
|
ixfr r31, f11
|
|
|
|
adds -1,r0, r25
|
|
|
|
.dual
|
|
fzchkl f24 , f14 , f26 // f14 -check with unfrigged f14
|
|
and 1, r22 , r18 // r18 = extras on rhs
|
|
|
|
//}}}
|
|
.txaligned_path: // above branches re-merge here
|
|
//{{{
|
|
form f0,f0 // clear merge to start up
|
|
or r0, r22 ,r31 // r31 = orig r22
|
|
faddp f8 ,f0,f0
|
|
shr 1, r22 , r22 // r22 now n of 2s
|
|
faddp f10 ,f0,f0
|
|
adds -2, r31, r0 // goto last few if r22 < 2
|
|
form f0, f28
|
|
bc .txlast_few
|
|
fnop
|
|
adds -1, r22 , r22 // corrected for autoincrement, so test -3 below
|
|
fnop
|
|
bla r25 , r22 , .txinner_loop
|
|
//}}}
|
|
|
|
//{{{ 32-bit f14 , texture inner loop, 2 pixels at a time
|
|
.txinner_loop_db:
|
|
fxfr f28 ,r31 // r31 = low pixel interpolated f8 , f10
|
|
fst.d f26 , 8( r17 ) // IMPORTANT - we cannot auto-increment
|
|
.txinner_loop:
|
|
fxfr f29 , r19 // in same cycle as fxfr ! ! ! ! !
|
|
fld.d 16( r17 ), f24
|
|
faddz f14 , f22 , f14
|
|
shr 2,r31,r31 // drop 2 of 4 blue bits, i.e word address
|
|
fzchks f0,f0,f0 // drop 4 more PM bits
|
|
shr 2, r19 , r19
|
|
fzchkl f0,f0,f0 // drop 2 more PM bits
|
|
fld.l r20 (r31), f30
|
|
faddp f8 , f16 , f8
|
|
fld.l r20 ( r19 ), f31
|
|
faddp f10 , f18 , f10
|
|
addu 8, r17 , r17 // see note on r17 ++ above
|
|
fnop
|
|
ld.c psr,r31 // r31 holds 16-bit pixel size
|
|
form f0, f28 // and merge the colour ready for next
|
|
xorh 0x00c0,r31, r19 // 0xc flips 32-16
|
|
fnop // r19 holds 32-bit pixelsize
|
|
st.c r19 , psr // goto 32 bits
|
|
fnop
|
|
pst.d f30 , 8( r16 )++ // do pixel store
|
|
fnop
|
|
st.c r31, psr // and go back to 16 bits
|
|
fnop
|
|
bla r25 , r22 ,.txinner_loop_db
|
|
fzchkl f24 , f14 , f26
|
|
nop
|
|
// weve exited the loop here
|
|
fnop
|
|
or r0, r18 ,r0
|
|
fnop
|
|
bc .tx_exit
|
|
//}}}
|
|
//{{{ there is just 1 pixel to go - we have a good f14 in f26 , and 2 good cols
|
|
.txlast_few: // we CANNOT ixfr and fxfr
|
|
fmov.ss f6 , f15
|
|
nop
|
|
fxfr f28 ,r31 // txtemp1 = interpolated f8 , f10
|
|
nop
|
|
fzchkl f24 , f14 , f26
|
|
shr 2,r31,r31
|
|
fzchks f0,f0,f0 // trash 4 PM bits
|
|
fld.l r20 (r31), f28
|
|
fzchkl f0,f0,f0 // and 2 more PM bits
|
|
fst.d f26 , 8( r17 )++
|
|
fnop
|
|
ld.c psr,r31
|
|
fnop
|
|
xorh 0x00c0,r31, r19
|
|
fnop
|
|
st.c r19 , psr
|
|
fnop
|
|
pst.d f28 , 8( r16 )++
|
|
fnop
|
|
st.c r31,psr
|
|
.tx_exit:
|
|
.enddual
|
|
form f0,f0
|
|
bri r1
|
|
form f0,f0
|
|
nop
|
|
|
|
|
|
//}}}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//}}}
|
|
//{{{ ftexline256 ( *fb, *zb, f8 , f10 , *tb, f14 , dx, f16 , f18 , DUMMY , f22 )
|
|
.globl _ftexline256
|
|
.align 8
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// WARNING - r18 and r19 overload ir and ig - be careful
|
|
|
|
_ftexline256::
|
|
|
|
fxfr f20 , r20
|
|
and 4, r16 ,r0 // if r16 &7 == 0, cc set
|
|
bc .txaligned256 // so we jump if r16 &7==0, i.e aligned
|
|
|
|
.txunaligned256: // ie first pixel NOT on a 64-bit boundary
|
|
//{{{
|
|
// align to double boundary
|
|
|
|
adds -12, r17 , r17
|
|
adds -12, r16 , r16
|
|
|
|
fld.d 8( r17 ), f24 // load zbuffer value (from &z0-4)
|
|
|
|
// correct for interpolant over-tick - first f8 , f10
|
|
|
|
subs r18 , r23 , r31
|
|
and 0xffff,r31,r31
|
|
ixfr r31, f8
|
|
|
|
and 0xffff, r18 ,r31
|
|
ixfr r31, f9
|
|
|
|
subs r19 , r24 , r31
|
|
and 0xffff,r31,r31
|
|
ixfr r31, f10
|
|
|
|
and 0xffff, r19 ,r31
|
|
ixfr r31, f11
|
|
|
|
ixfr r21 , f15
|
|
|
|
adds -1,r0, r25
|
|
fmov.ss f6 , f14 // important - zlo MUST be invisible for fchkz
|
|
|
|
adds 1, r22 , r22 // tick count
|
|
|
|
fzchkl f24 , f14 , f26 // f14 -check with frigged f14
|
|
subs r21 , r26 , r31
|
|
and 1, r22 , r18 // r18 = extras on rhs
|
|
br .txaligned_path256
|
|
ixfr r31, f14 // correct f14
|
|
//}}}
|
|
.txaligned256: // ie first pixel IS on a 64-bit boundary
|
|
//{{{
|
|
//
|
|
// write r21 into dbl f14 lo, r21 + f22 into dbl f14 hi etc
|
|
//
|
|
adds -8, r17 , r17
|
|
adds -8, r16 , r16
|
|
|
|
fld.d 8( r17 ), f24 // load zbuffer value HOURS to complete
|
|
|
|
ixfr r21 , f14
|
|
adds r21 , r26 , r31
|
|
ixfr r31, f15 // this needs 3 cycles to complete before fzchkl
|
|
|
|
ixfr r18 , f8
|
|
addu r18 , r23 , r31
|
|
ixfr r31, f9
|
|
|
|
ixfr r19 , f10
|
|
addu r19 , r24 , r31
|
|
ixfr r31, f11
|
|
|
|
adds -1,r0, r25
|
|
|
|
.dual
|
|
fzchkl f24 , f14 , f26 // f14 -check with unfrigged f14
|
|
and 1, r22 , r18 // r18 = extras on rhs
|
|
|
|
//}}}
|
|
.txaligned_path256: // above branches re-merge here
|
|
//{{{
|
|
form f0,f0 // clear merge to start up
|
|
or r0, r22 ,r31 // r31 = orig r22
|
|
faddp f8 ,f0,f0
|
|
shr 1, r22 , r22 // r22 now n of 2s
|
|
faddp f10 ,f0,f0
|
|
adds -2, r31, r0 // goto last few if r22 < 2
|
|
form f0, f28
|
|
bc .txlast_few256
|
|
fnop
|
|
adds -1, r22 , r22 // corrected for autoincrement, so test -3 below
|
|
fnop
|
|
bla r25 , r22 , .txinner_loop256
|
|
//}}}
|
|
|
|
//{{{ 32-bit f14 , texture inner loop, 2 pixels at a time
|
|
.txinner_loop_db256:
|
|
fxfr f28 ,r31 // r31 = low pixel interpolated f8 , f10
|
|
fst.d f26 , 8( r17 ) // IMPORTANT - we cannot auto-increment
|
|
.txinner_loop256:
|
|
fxfr f29 , r19 // in same cycle as fxfr ! ! ! ! !
|
|
fld.d 16( r17 ), f24
|
|
faddz f14 , f22 , f14
|
|
shr 6,r31,r31 // drop 6 of 8 blue bits, i.e word address
|
|
fzchks f0,f0,f0 // drop 4 more PM bits
|
|
shr 6, r19 , r19
|
|
fzchkl f0,f0,f0 // drop 2 more PM bits
|
|
fld.l r20 (r31), f30
|
|
faddp f8 , f16 , f8
|
|
fld.l r20 ( r19 ), f31
|
|
faddp f10 , f18 , f10
|
|
addu 8, r17 , r17 // see note on r17 ++ above
|
|
form f0, f28 // and merge the colour ready for next
|
|
pst.d f30 , 8( r16 )++ // do pixel store
|
|
fnop
|
|
bla r25 , r22 ,.txinner_loop_db256
|
|
fzchkl f24 , f14 , f26
|
|
nop
|
|
// weve exited the loop here
|
|
fnop
|
|
or r0, r18 ,r0
|
|
fnop
|
|
bc .tx_exit256
|
|
//}}}
|
|
//{{{ there is just 1 pixel to go - we have a good f14 in f26 , and 2 good cols
|
|
.txlast_few256: // we CANNOT ixfr and fxfr
|
|
fmov.ss f6 , f15
|
|
nop
|
|
fxfr f28 ,r31 // txtemp1 = interpolated f8 , f10
|
|
nop
|
|
fzchkl f24 , f14 , f26
|
|
shr 6,r31,r31
|
|
fzchks f0,f0,f0 // trash 4 PM bits
|
|
fld.l r20 (r31), f28
|
|
fzchkl f0,f0,f0 // and 2 more PM bits
|
|
fst.d f26 , 8( r17 )++
|
|
fnop
|
|
pst.d f28 , 8( r16 )++
|
|
.tx_exit256:
|
|
.enddual
|
|
form f0,f0
|
|
bri r1
|
|
form f0,f0
|
|
nop
|
|
|
|
|
|
//}}}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//}}}
|
|
|
|
//{{{ 32-bit f14 , 32-bit pixel inner loop OPENED out in 4s
|
|
// .inner4_loop:
|
|
// pfaddz f14 , f22 ,f0
|
|
// fld.d 16(zaddr), dbltemp
|
|
// pfzchkl dbltemp, f14 , f14
|
|
// nop
|
|
// pfaddz f14 , f22 ,dbltemp
|
|
// fst.d f26 , 8(zaddr)
|
|
// pfzchkl f0,f0, f14 // now 4 pixels worth of mask is ready
|
|
// nop
|
|
// faddp f12 , f20 , f12
|
|
// fst.d dbltemp, 16(zaddr)++
|
|
// faddp f10 , f18 , f10
|
|
// nop
|
|
// faddp f8 , f16 , f8
|
|
// pst.d f28 , 8(paddr)++
|
|
// form f0, f28
|
|
// nop
|
|
// faddp f12 , f20 , f12
|
|
// nop // adds -4, dx, dx
|
|
// faddp f10 , f18 , f10
|
|
// pst.d f28 , 8(paddr)++
|
|
// faddp f8 , f16 , f8
|
|
// nop
|
|
// form f0, f28
|
|
// bla minus1,dx,.inner4_loop // bnc.t .inner4_loop
|
|
// fzchkl f24 , f14 , f26
|
|
// nop
|
|
// // weve exited the loop here
|
|
// fnop
|
|
// or r0,itemp3,r0 // for exit condition code
|
|
// fnop
|
|
// bc .zb_exit
|
|
//}}}
|
|
//{{{ 32-bit f14 , flat pixel inner loop OPENED out in 4s
|
|
// .flat4_loop:
|
|
// pfaddz f14 , f22 ,f0
|
|
// fld.d 16(zaddr), dbltemp
|
|
// pfzchkl dbltemp, f14 , f14
|
|
// fst.d f26 , 8(zaddr)
|
|
// pfaddz f14 , f22 ,dbltemp
|
|
// nop
|
|
// pfzchkl f0,f0, f14 // now 4 pixels worth of mask is ready
|
|
// fst.d dbltemp, 16(zaddr)++
|
|
// fnop
|
|
// pst.d f28 , 8(paddr)++
|
|
// fnop
|
|
// pst.d f28 , 8(paddr)++
|
|
// fnop
|
|
// bla minus1,dx,.flat4_loop
|
|
// fzchkl f24 , f14 , f26
|
|
// nop
|
|
// // weve exited the loop here
|
|
// fnop
|
|
// or r0,itemp3,r0 // for exit condition code
|
|
// fnop
|
|
// bc .zb_exit
|
|
//}}}
|
|
|
|
|
|
//{{{ setpixelsize
|
|
//
|
|
// Set pixel width - 00 == 8 bits
|
|
// 01 == 16
|
|
// 10 == 32
|
|
//
|
|
//
|
|
|
|
PSRMASK = 0x00c0
|
|
|
|
.globl _setpixelsize
|
|
_setpixelsize::
|
|
|
|
ld.c psr,r31
|
|
andnoth PSRMASK,r31,r31
|
|
shl 22,r16,r16
|
|
or r16,r31,r31
|
|
st.c r31,psr
|
|
bri r1
|
|
or r31, r0, r16
|
|
|
|
//}}}
|
|
|
|
//{{{ getpixelsize
|
|
//
|
|
// Set pixel width - 00 == 8 bits
|
|
// 01 == 16
|
|
// 10 == 32
|
|
//
|
|
//
|
|
|
|
PSRMASKALL = 0x00c0
|
|
|
|
.globl _getpixelsize
|
|
_getpixelsize::
|
|
|
|
ld.c psr,r31
|
|
andh PSRMASKALL,r31,r31
|
|
bri r1
|
|
shr 22,r31,r16
|
|
|
|
//}}}
|
|
|
|
//{{{ setdirectmode
|
|
|
|
|
|
.globl _setdirectmode
|
|
_setdirectmode::
|
|
|
|
ld.c dirbase,r31
|
|
and -2,r31,r31
|
|
st.c r31,dirbase
|
|
|
|
bri r1
|
|
nop
|
|
|
|
//}}}
|
|
|
|
//{{{ clear store
|
|
|
|
//
|
|
// Clear Store
|
|
//
|
|
// assumes .quad aligned data
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//
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.globl _clear_store
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_clear_store::
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ixfr r17,f16
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ixfr r17,f17
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ixfr r17,f18
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ixfr r17,f19
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|
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adds -16,r18,r18
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adds -16,r0,r19 // loop increment
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bla r19,r18,init_loop
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addu -16,r16,r16 // adjust address for autoincrement
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init_loop:
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bla r19,r18,init_loop
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fst.q f16,16(r16)++
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bri r1
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nop
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//}}}
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//{{{ thrash
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|
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//
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|
// thrash
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|
//
|
|
//
|
|
// thrash (loation, times)
|
|
//
|
|
//
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|
|
|
.globl _thrash
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|
_thrash::
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|
|
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adds -1, r0, r18
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|
|
|
ixfr r18,f8
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|
bla r18,r17,thrash_loop
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|
nop
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|
|
|
thrash_loop:
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|
|
|
fld.l r0(r16),f8
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|
bla r18,r17,thrash_loop
|
|
fst.l f8,r0(r16)
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|
|
|
bri r1
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|
nop
|
|
//}}}
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|
|
|
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// this is the end
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|
.data
|