CydandClaude Fable 5
db7745fcd0
Un-ignored: the dev drive is the ground truth the restoration and emulator work constantly reference (DPL3/LIBDPL + VRENDER i860 renderer source, BT/RP live+dev game trees, VGL_LABS pod boot, scene/audio content). Kept in-repo for the pod-owner community. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
441 lines
13 KiB
C++
441 lines
13 KiB
C++
/*{{{ decls associated with DIVISION pxpl5 implementation*/
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#define divpl5_xshift 6
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#define divpl5_yshift 7
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/*}}} */
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/*{{{ on pxpl5 oddness*/
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/*
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pxpl5 forces you to do 3 things you normally wouldnt do on
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a graphics system - edgeize, planarize and binitize primitives
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edgeizing involves turning a polygon into a set of edges, each
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edge described by an expression of the form f(x,y) = Ax + By + C,
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where conventionally a point is INSIDE the edge if f(x,y) > 0 at (x,y)
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planarization is pretty similar, and is used for Z-buffering,
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Gouraud-shading and texturing. Planarization involves computing a
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screen-space planar equation for a given variable - so to Z-buffer,
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Gouraud-shade and texture a triangle we need to compute
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Z=fz(x,y), r=fr(x,y), g=fg(x,y), b=fb(x,y), u=fu(x,y), v=fv(x,y)
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where each of fz, fr, fg, fb, fu, fv are cast as expression of the form
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f=Ax + By + C
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binitization is different, and stems from the original MIMDness of pxpl5 -
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rather than build a 640x512 array of pixel-processors, we use multiple
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arrays of 128x128 (or 64x128) and if the polygons scatter statistically
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well, we can get many times more performance for a given number of
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pixel-processors
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in order to do this, as a triangle is transformed to screen-space, we need
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to determine how many screen-space regions of 64x128 are overlapped by the
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triangle, and place the triangle into 'bins' associated with each region.
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binitization may kill me yet.
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*/
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/*}}} */
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/*{{{ typedefs for planarization*/
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typedef struct s_bininfo {
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int bin_minx;
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int bin_miny;
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int bin_maxx;
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int bin_maxy;
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} bininfo;
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typedef struct s_preplane {
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float x23;
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float x31;
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float x12;
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float C;
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} preplane;
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/*}}} */
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/*{{{ void edgeize ( float *eqn, float *p1, float *p2 )*/
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void edgeize ( float *eqn, float *p1, float *p2 )
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{
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/* *********************
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takes 2 point p1 and p2 and computes the edge
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equation edge Ax + By + C, +ve inside, -ve outside
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the edge
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4 cases -
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a) p0 b) p1
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\ /
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\ /
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\ /
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p1 p0
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c) p1 d) p0
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\ /
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\ /
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\ /
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p0 p1
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We need to ensure that in all cases we treat the edges identically,
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e.g a = c with flipped vertices / opcode, ditto b, d
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*/
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float A, B, C;
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/*
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however, 1st approximation - this will suffer
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rounding errors + DDA cracks
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*/
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eqn[0]=p1[Y] - p2[Y];
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eqn[1]=p2[X] - p1[X];
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eqn[2]=(p2[Y]*p1[X]) - (p2[X]*p1[Y]);
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}
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/*}}} */
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/*{{{ on planarization*/
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/*
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Examination of the equations for planarization, and the UNC rendering
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library, indicates some useful speedups for planarizing.
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A recurring term is the divisor for all 3 coefficients, termed C. This
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is independent of the planarized variable; it only varies with screen-space
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X and Y, so can be precomputed once per triangle and re-used for
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all planarized expressions
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ditto some recurring difference expressions (x1 - x2 etc.)
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So preplanarize precomputes the useful stuff into a structure for
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subsequent planarizing. Ideally of course we precompute this into
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a set of floating-point registers. Later.
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Or maybe right now - how many registers do I need to do this?
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rx23 \
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rx31 > the recurring differences
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rx12 /
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rC the divisor for preplanarizing; now to planarize, strive to keep
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rv1y
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rv2y
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rv3y
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rv1x
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rv2x and
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rv3x in registers also
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so we keep 10 fp registers hanging around, so to planarize a variable
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we access memory 3 times, to load
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v1
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v2
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v3 (which are used many times) using up just 13 fp registers
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then 3 writes to eqn->A, eqn->B, eqn->C
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this should be very fast indeed on an XP
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The correct structure for the code is probably a dispatch vector of
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C functions associated with each type of triangle - e.g 24-bit Gouraud,
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8-bit Gouraud + intrinsic + spec
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8-bit Gouraud + intrinsic + spec + texture + MIP etc,
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the function calls an assembly stub which preplanarizes, then
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repeatedly calls an assembly-coded planarize as many times as needed
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Planarization looks like a cost of 25 ticks per planarized variable,
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so we can planarize
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Z, diffuse, spec in 1.5 uS (667k triangles/sec)
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Z, diffuse, spec, u, v, homo in 3uS (333k )
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Z, diffuse, spec, u, v, homo, MIP in 3.5uS, or (286k )
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it looks like we can edgize in about 20 ticks per edge, or 1.2 uS per
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triangle, so the edgize / planarize costs become
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Z, diffuse, spec in 2.7 uS (370k triangles/sec)
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Z, diffuse, spec, u, v, homo in 4.2 uS (238k )
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Z, diffuse, spec, u, v, homo, MIP in 3.5uS, or (212k )
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or the VWE benchmark of flat-shaded textured quads -
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Z, u, v, homo, MIP in 3.6uS or (278k )
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SO we are in shape performance-wise for planarization. How is binitizing.
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Read on.
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*/
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/*}}} */
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/*{{{ void preplanarize ( float *coeffs, preplane *p, float *v1, float *v2, float *v3 )*/
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void preplanarize ( float *coeffs, preplane *p, float *v1, float *v2, float *v3 )
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{
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p->x23=v2[X] - v3[X];
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p->x31=v3[X] - v1[X];
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p->x12=v1[X] - v2[X];
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p->C=1.0f / ((v1[X] * (v2[Y] - v3[Y])) +
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(v2[X] * (v3[Y] - v1[Y])) +
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(v3[X] * (v1[Y] - v2[Y])));
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}
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/*}}} */
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/*{{{ void planarize ( float *eqn, float *v1, float *v2, float *v3, int index, preplane *p )*/
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void planarize ( float *eqn, float *v1, float *v2, float *v3, int index, preplane *p )
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{
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eqn[0]=-p->C* ((v1[Y] * (v2[index] - v3[index])) +
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(v2[Y] * (v3[index] - v1[index])) +
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(v3[Y] * (v1[index] - v2[index])));
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eqn[1]=-p->C*((v1[index] * p->x23) +
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(v2[index] * p->x31) +
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(v3[index] * p->x12));
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eqn[2]= p->C*((v1[X]*((v2[Y]*v3[index]) - (v3[Y]*v2[index]))) +
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(v2[X]*((v3[Y]*v1[index]) - (v1[Y]*v3[index]))) +
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(v3[X]*((v1[Y]*v2[index]) - (v2[Y]*v1[index]))));
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}
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/*}}} */
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/*{{{ binitizing*/
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/*{{{ datastructures for binitizing*/
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/* *********************************
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what are the best datastructures for binitizing ?
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they need working out in conjunction with the DMA engine
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protocol
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the DMA engine takes, per bin, an array of 64-bit words, organised as
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address:count|opcode
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the address is where the IGC data resides, the count is the no of
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64-bit words in the IGC packet. The packet could be typically a
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triangle, a partial triangle, a sphere or a chunk of end-of-frame data
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triangles are 30-40 32-bit words long.
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a screen may be anything from 512 to 1280 pixels wide, which is from 8
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to 64 bins wide, typically 10 (NTSC) - awkward, needs * rather than <<
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a typical bin data looks like
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address:count
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address:count
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address:count
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...
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address:count
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in contiguous memory locations. How to assemble these live with
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minimal mallocing?
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YEAH - good one hardware guys. The macro language supports a GOTO;
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so we simply malloc chunks of say 32 64-bit words, and the last one
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contains GOTO next chunk. So we never need to memcpy. In fact in the
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steady-state we never need to malloc.
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So if we have to render a triangle, we have to put its IGC data into
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memory, then reference this data from multiple bin lists. All rendered
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triangles can be put into a huge pool (double-buffered), which is
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just incremented.
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So we have the structures in place - how do we binitize?
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Lets render a triangle -
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pre --> enable voodoo 1
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edge 4
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edge 4
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edge 4
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z compare 4
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z replace 4
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lum 4
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spec 4
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scalar_stuff 1
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p -->
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We need to place pre:42 (pre:21?) into all the bins the triangle overlaps
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For each bin we need a head chunk, and a tail chunk. Each chunk contains a
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count (so I know where to put the next triangle).
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I think I am starting to understand how to do this ...
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*/
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/*}}} */
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/*{{{ typedefs / decls for binitization*/
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#define BIN_FULL (63*2) /* when index==this, chain into next chunk */
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typedef struct s_binchunk {
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double DMA_opcodes[64]; /* force dbl-alignment, 64 triangles worth */
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int usage; /* in 32-bit words, always dbl-bumped */
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struct s_binchunk *next; /* only used for housekeeping */
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} binchunk;
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typedef struct s_screenbin {
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binchunk *head;
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binchunk *tail;
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} screenbin;
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binchunk *free_binchunks=NULL;
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screenbin *screen0bins=NULL,
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*screen1bins=NULL,
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*screenbins =NULL;
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int DMAscreen=0, writeScreen=1;
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/*}}} */
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/*{{{ void create_screenbins ( int screenx, int screeny )*/
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void create_screenbins ( int screenx, int screeny )
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{
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int binsx=screenx >> divpl5_xshift;
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int binsy=screeny >> divpl5_yshift;
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screen0bins=(screenbin *) malloc (binsx*binsy*sizeof(screenbin));
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screen1bins=(screenbin *) malloc (binsx*binsy*sizeof(screenbin));
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screenbins=screen0bins;
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}
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/*}}} */
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/*{{{ void liberate_screenbins ( screenbin *screenbins, int screenx, int screeny )*/
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void liberate_screenbins ( screenbin *screenbins, int screenx, int screeny )
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{
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/*
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take the whole screen and put it back onto the free list, EXCEPT for
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1st chunk in each screen region
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*/
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int i, j;
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for (i=0; i<screenx; i++ ) {
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for (j=0; j<screeny; j++ ) {
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binchunk *chunk=screenbins->head;
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if (chunk == NULL) {
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printf ("Error, initially empty region in liberate_screenbins\n" );
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}
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chunk->usage=0;
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chunk=chunk->next;
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while (chunk) {
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binchunk *nxt=chunk->next;
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chunk->next=free_binchunks;
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chunk=nxt;
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}
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screenbins++;
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}
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}
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}
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/*}}} */
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/*{{{ void grab_binchunks ( int grab_chunks )*/
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void grab_binchunks ( int grab_chunks )
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{
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/* mallocs and inits an initial tranche of binchunks */
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int i;
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for (i=0; i<grab_chunks; i++ ) {
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binchunk *bin,
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*prev=free_binchunks;
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bin=(binchunk *) malloc( sizeof (binchunk));
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if (bin == NULL) {
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printf ("Malloc failed in grab_binchunk\n" );
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}
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bin->usage=0;
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bin->next=prev;
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prev=bin;
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}
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}
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/*}}} */
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/*{{{ binchunk *next_binchunk ()*/
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binchunk *next_binchunk ()
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{
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if (free_binchunks == NULL)
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grab_binchunks();
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free_binchunks=free_binchunks->next;
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return free_binchunks;
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}
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/*}}} */
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/*{{{ void binitize ( int macro_lo, int macro_hi,*/
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void binitize ( int macro_lo, int macro_hi,
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float fminx, float fminy,
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float fmaxx, float fmaxy,
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int screen_maxx, int screen_maxy,
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int screen_bins_x )
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{
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/*
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binitizes a primitive of known screen-space extents
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the DMA engine macros associated with the primitive are held
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in macro_lo, macro_hi - typically { SEND macro_address,size }
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the screen-space extents are held in fminx .. fmaxy, and
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the integer screen resolution is held in screen_maxx, screen_maxy,
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with (optimization) the bin-count in the x-direction held in
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screen_bins_x
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To binitize, we first work out what is the lower left corner bin,
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then outer loop in y, inner loop x, dropping the macro into all
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encountered bins.
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*/
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int minx, miny,
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maxx, maxy;
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minx=(int) fminx;
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miny=(int) fminy;
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maxx=(int) fmaxx;
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maxy=(int) fmaxy;
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if (maxx < 0) return;
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if (maxy < 0) return;
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if (minx > screen_maxx) return;
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if (miny > screen_maxy) return;
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minx >>= divpl5_xshift;
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miny >>= divpl5_yshift;
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maxx >>= divpl5_xshift;
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maxy >>= divpl5_yshift;
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/*
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so we have minimax xy in screen-space bin indices -
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put the data into bins
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*/
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{
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/* get 1st bin */
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screenbin *top_left_bin=&screenbins[(miny*screen_bins_x) + minx];
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screenbin *sbin=top_left_bin, *lbin=sbin;
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screenbin *xbin=lbin;
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register int x;
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/* scan down all y bins */
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while (y < maxy) {
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/* scan across all x bins */
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for (x=maxx; x; x-- ) {
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/* add doubleword macro to bin */
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binchunk *bin=sbin->tail;
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register int usage=bin->usage;
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if (bin->usage == BIN_FULL) {
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binchunk *nextbin=*next_binchunk ();
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bin->DMA_opcodes[usage++]=(int) nextbin;
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bin->DMA_opcodes[usage++]=DMA_GOTO;
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bin=nextbin;
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sbin->tail=bin;
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usage=0;
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}
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bin->DMA_opcodes[usage++]=macro_lo;
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bin->DMA_opcodes[usage++]=macro_hi;
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bin->usage=usage;
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xbin++;
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}
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lbin+=screen_bins_x;
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}
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}
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}
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/*}}} */
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/*}}} */
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