CydandClaude Fable 5
db7745fcd0
Un-ignored: the dev drive is the ground truth the restoration and emulator work constantly reference (DPL3/LIBDPL + VRENDER i860 renderer source, BT/RP live+dev game trees, VGL_LABS pod boot, scene/audio content). Kept in-repo for the pod-owner community. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
253 lines
6.3 KiB
Scheme
253 lines
6.3 KiB
Scheme
//
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// Define EDGE structure
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//
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// .dsect
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#define EDGE_ex 0
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#define EDGE_ez 4
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#define EDGE_ec 8
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#define EDGE_edx 12
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#define EDGE_edz 16
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#define EDGE_edc 20
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// .end
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//
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// scanSegment( char *framebufer, short int *zbuffer,
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// int y0, int yend,
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// EDGE *left, EDGE *right, int dzBydx,
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// processor_bits, processor_id, STEP
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// )
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//
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// Parameters:
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#define p_fbuffer r16
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#define p_zbuffer r17
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#define p_y0 r18
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#define p_yend r19
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#define p_leftE r20
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#define p_rightE r21
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#define p_dzBydx r22
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#define processor_bits r23
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#define processor_id r24
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#define STEP r25
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//
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// Locals:
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#define pixline r4
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#define zixline r5
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#define nlines r6
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#define zbuffer r7
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#define fbuffer r8
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#define leftE r9
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#define rightE r10
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#define left_ex r11
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#define right_ex r12
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#define right_ez r13
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#define save_1 r14
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#define save_2 r15
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#define save_3 r7
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#define zaddr r16
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#define paddr r17
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#define left_ez r18
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#define dz r19
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#define x0 r20
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#define dx r21
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#define left_ec r22
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#define mask r23
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#define y0 r26
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#define y00 r27
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//
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.globl _scanSegment
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.text
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_scanSegment::
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// Save return address
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addu -80,sp,sp
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st.l r1, 0(sp)
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st.l r4,4(sp)
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st.l r5,8(sp)
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st.l r6,12(sp)
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st.l r7,16(sp)
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st.l r8,20(sp)
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st.l r9,24(sp)
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st.l r10,28(sp)
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st.l r11,32(sp)
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st.l r12,36(sp)
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st.l r13,40(sp)
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st.l r14,44(sp)
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st.l r15,48(sp)
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// copy parameters to ease call to zbufferSegment
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or p_fbuffer,r0,fbuffer
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or p_zbuffer,r0,zbuffer
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or p_y0,r0,y0
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subs p_yend,p_y0,nlines // nlines = yend-y0
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or p_leftE,r0,leftE
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or p_rightE,r0,rightE
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or p_dzBydx,r0,dz
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//
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// y00 = y0 >> processor_bits
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// mask = (1<<processor_bits) -1;
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//
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// pixline = fbuffer + STEP * y00
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// zixline = zbuffer + STEP * y00
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//
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shr processor_bits, y0, y00
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or 1, r0, itemp1
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ixfr STEP, f2 // copy STEP and y00 to fp regs
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ixfr y00, f4 // for multiply
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shl processor_bits, itemp1, mask
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adds -1, mask, mask
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fmlow.dd f4, f2, f6 // do STEP * y00
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fxfr f6, itemp1
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addu itemp1,fbuffer,pixline
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addu itemp1,zbuffer,zixline
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// load stuff left_ec same reg as Col
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ld.l EDGE_ex(leftE),left_ex
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ld.l EDGE_ex(rightE),right_ex
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ld.l EDGE_ez(leftE),left_ez
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ld.l EDGE_ez(rightE),right_ez
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ld.l EDGE_ec(leftE),Col
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adds 1,nlines,nlines // anticipate decrement
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// For each scanline
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next_scan_line:
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// WHILE nlines>0 LOOP
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adds -1,nlines,nlines
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bte r0,nlines,exit_scanSegment
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//
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// If (y0 &mask != processor_id ) continue;
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//
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and y0,mask, itemp1
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bte itemp1,processor_id,ignore_line
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// dx=(right->ex)>>16-(left->ex)>>16
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shr 16,left_ex,x0 // descale left edge to temp
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shr 16,right_ex,dx // descale right edge to dx
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subs dx,x0,dx // form right-left
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// if (dx==0) then ignore this line, walk edges (not a delayed br )
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bte r0, dx, ignore_line
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subs r0, dx, r0 // if (dx<0) swap pointers etc..
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bc no_swap
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// swap l / r values
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subs r0,dx,dx // dx = -dx
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or leftE,r0,itemp1
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or rightE,r0,leftE
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or itemp1,r0,rightE
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or left_ex,r0,itemp1
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or right_ex,r0,left_ex
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or itemp1,r0,right_ex
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or left_ez,r0,itemp1
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or right_ez,r0,left_ez
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or itemp1,r0,right_ez
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shr 16,left_ex,x0
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no_swap:
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// pixel = pixline+x0
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addu pixline,x0,paddr
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// pixel = pixel&0xfffffff8
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andnot 0x7,paddr,paddr
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// zixel = zixline+x0
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shl 1,x0,itemp1
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addu zixline,itemp1,zaddr
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// zixel = zixel&0xfffffff0
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andnot 0xf,zaddr,zaddr
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// try to avoid any memory hits here
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or r0,dz,save_1
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or r0,x0,save_2
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call _zbufferSegment // this is a delayed op
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or r0,left_ez,save_3
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or r0,save_1,dz
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or r0,save_2,x0
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or r0,save_3,left_ez
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ignore_line:
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// walk up edges of screen
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ld.l EDGE_edx(leftE),itemp1 // dx and dz are contiguous fields
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adds left_ex,itemp1,left_ex
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ld.l EDGE_edz(leftE),itemp1 // dx and dz are contiguous fields
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adds left_ez,itemp1,left_ez
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ld.l EDGE_edx(rightE),itemp1
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adds right_ex,itemp1,right_ex
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ld.l EDGE_edz(rightE),itemp1
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adds right_ez,itemp1,right_ez
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//
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//
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// if((y0 & mask) == mask)
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// {
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// pixline += STEP;
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// zixline += STEP;
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// }
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//
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and y0,mask,itemp1
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btne itemp1, mask, NoStep
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adds pixline, STEP, pixline
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adds zixline, STEP, zixline
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NoStep:
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br next_scan_line
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// delayed branch
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adds 1,y0,y0
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exit_scanSegment:
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// restore registers into edge structures
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st.l right_ex,EDGE_ex(rightE)
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st.l right_ez,EDGE_ez(rightE)
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st.l left_ex, EDGE_ex(leftE)
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st.l left_ez, EDGE_ez(leftE)
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// restore local registers
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ld.l 4(sp), r4
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ld.l 8(sp), r5
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ld.l 12(sp), r6
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ld.l 16(sp), r7
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ld.l 20(sp), r8
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ld.l 24(sp), r9
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ld.l 28(sp), r10
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ld.l 32(sp), r11
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ld.l 36(sp), r12
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ld.l 40(sp), r13
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ld.l 44(sp), r14
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ld.l 48(sp), r15
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// restore return address
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ld.l 0(sp), r1
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bri r1
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addu 80,sp,sp
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