CydandClaude Fable 5
f236d15d51
The VPX responder device now drives production BattleTech v4.10 through the full transputer/i860 boot, far past the Phase 1 wall: - iserver boot handshake solved: feeds 3 well-formed 'version' (tag 42) iserver requests, satisfying startup_handshake()'s 3 transactions. - i860 download solved: parses the outbound framed renderer messages (vr_860args/code/data/bss) and absorbs them, staying byte-aligned. - echo-action reply model validated against board source (VRENDER/VR_REMOT.C reply() echoes the received action); device tracks and echoes the last outbound action generally. Remaining sub-protocol identified and characterized: after i860 boot the host switches to a FIFO fast path (OUTSW.ASM: 0x40 tag + REP OUTSW 16-bit words to FIFO port 0x154/0x155, gated by ok_to_fifo at 0x160). The current build stops at velocirender_sync because the device only implements the slow byte path. PHASE2-PROGRESS.md documents the exact next steps (FIFO transport + render loop -> Phase 3 OpenGL backend). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
27 lines
477 B
Plaintext
27 lines
477 B
Plaintext
[sdl]
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output=opengl
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[dosbox]
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memsize=32
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machine=svga_s3
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[cpu]
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core=normal
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cputype=pentium
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cycles=20000
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[serial]
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serial1=disabled
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serial2=disabled
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[autoexec]
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mount c "image"
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c:
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set L4CONTROLS=RIO,KEYBOARD
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set L4TIMER=
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set BLASTER=A220 I5 D1 H5 P330 T6
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set VIDEOFORMAT=svga
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set TEMP=c:\
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set DPLARG=/tranny~.\vrendmon.btl~/i860~.\vrnostex.mng~/device~0x150~/video~svga~/pipes~1~/qual~0x14~/system_tex~0~
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32rtm.exe -x
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btl4opt.exe -egg test.egg
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32rtm.exe -u
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echo RESPOND-DONE
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pause
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