riojoy/docs/hardware

RIO cockpit hardware — boards, schematics, GAL dump

Physical documentation of the VWE Tesla-cockpit RIO (Remote Input/Output) board set, gathered during the 2026 restoration: board photos (Signal, 2026-07-15), a scan of the original paper wire schematics, and the fuse map read out of the RIO board's GAL address decoder.

All boards are Copyright 1994 V.W.E. Inc. — the schematic title blocks spell it out: Virtual World Entertainment, 1100 W Cermak Suite B404, Chicago, Illinois, every sheet and silkscreen credited "Design by M.C." Schematic plots are dated 1/11/1996 (peripheral boards) and 6/26/1996 (RIO board), so these drawings post-date the Rev. 0/1 boards they describe.

Board family

P/N	Title	Rev photographed	Key silicon
1407	RIO board ("CPU board")	Rev. 3	Toshiba TMP68HC11 @ 8 MHz, GAL20V8A decoder, 27C512 EPROM, LH52B256 32K SRAM, 5× HCTL-2016
1401	Buttons board	Rev. 0	2× UCN5821A lamp drivers, 2× 74HCT165, 74HCT164, 74LS00/05
1402	Keypad board	Rev. 1	2× 74HCT164, CD74HCT165, 74LS00/05
1408	Display board ("RIO external display")	Rev. 1	Intersil ICM7228B 8-digit driver, 8× LTS313A 7-segment
1413	Quad Amplifier Board	Rev. 1	Pyramid PB-150P "Pro Plus" car amp (bolt-on) + passive 3-way crossovers

Plus the cockpit position sensors: HP HEDS-5700 two-channel quadrature optical encoders (option code I = 512 counts/rev; the photographed unit is date-coded 9515, Singapore), one per analog axis, read by the five HCTL-2016 counters on the RIO board (OPT1–OPT5 = stick X/Y, throttle, left/right pedals).

RIO board 1407 (schematic sheets 1–3, RIO_1407)

Sheet 1 — CPU : Memory Decoder. The TMP68HC11 runs in expanded multiplexed mode: a 74HCT573 latches A[0:7] off the AD bus, and U7 — drawn as a 20L8, fitted as a GAL20V8A-15LP — decodes A[8:15] into ROM_SEL* (27C512 EPROM, U10), RAM_SEL* (LH52B256-70LL 32K SRAM, U11), PH_SEL* (HCTL-2016 bank via two 74LS138s), DSP_SEL* (external display port) and BND_SEL (I/O-interface latch, sheet 3). Each HCTL-2016 feeds a 5-pin header (J4–J8) carrying CHA/CHB from a HEDS-5700. The DB9 COM port goes through a MAX231/MAX232-class level shifter; the schematic's IN_RESET* from the serial side is the hardware behind the DTR reset pulse described in PROTOCOL.md §1. The "display interface" block (ALS541 buffers, HEADER14) exports latched data lines HD[00:04] + digit address AS0-2 to the display board — this is a memory-mapped port, not the pod bus. A 22V10 site (U31) is drawn mostly N/C and is unpopulated on the photographed board.

Sheet 2 — Power & Reset Interface. A MAX690 supervisor provides power-fail reset and a watchdog (WDI); reset can also come from the front-panel RESET toggle (SW1) or remotely through an H11L1 optocoupler fed from an isolated 3-pin +5 VDC input (J8) — the game PC can hard-reset the board. The ABORT toggle (SW2) pulls the HC11 IRQ*. A 74LS241 drives the status LED bank: POWER ON, FAULT, RESET, RUN, TX, RX. Power enters on J9 through 5 A/10 A fuses, LC filters and 1N5341B clamp zeners, producing separate logic VCC and peripheral VCC_EXT rails.

Sheet 3 — I/O Interface ("pod bus"). Eight identical 16-pin IDC ports (J11–J18) fan out through ALS541 buffers and SIP resistor packs. All ports share the outbound signals; each port has its own return line (DI[0..7], selected by a 74LS138 from SEL0-2) and its own buffered brightness line (BRT_CTR0-7, all copies of one PWM signal). A 74HC574 latch written via BND_SEL holds the bus control bits (SEL0-2, RD_SB, WR_SB, D_OUT, CCK) — so the firmware bit-bangs the bus by rewriting this latch.

Pod bus signal set (per port)

Signal	Direction	Purpose
CCK	RIO → pod	shift clock
DD_IN	RIO → pod	serial data into the pod's 74HCT164s (address select + payload)
WR_SB	RIO → pod	write strobe (latch lamp/display data)
RD_SB	RIO → pod	read strobe (parallel-load the pod's 74HCT165)
DD_OUT	pod → RIO	serial readback, open-collector 74LS05 so pods can share a cable
BRT_CTR	RIO → pod	global lamp-brightness PWM, gates the UCN5821A output enable
VCC_EXT, GND	—	peripheral power rail

Every pod board carries a 74HCT164 whose parallel outputs go to an ADR. SEL. jumper block (A-0…A-7): the RIO shifts an address pattern down the cable, the jumper picks which bit this board answers to, and 74LS00 gates qualify RD_SB/WR_SB with that selection. This hardware addressing is what the 0x00–0x6F logical input map in PROTOCOL.md ultimately resolves to.

Peripheral boards

• 1401 Buttons board (PBE_1401) — eight 4-pin connectors (J3–J10), pinout 1 = buttons GND, 2 = button in, 3 = lamps +5V, 4 = lamps logic GND. Two UCN5821A serial-in latched sink drivers light the button lamps (brightness = BRT_CTR PWM on their OE), two 74HCT165s read the buttons back, one of them also echoing board status/address.
• 1402 Keypad board (KEY_1402) — hosts the COTS 16-key hex pad (0–F) on an 8-line header (4×4 matrix). A second 74HCT164 drives the matrix rows through open-collector 74LS05 inverters; the 74HCT165 reads the four columns (IN0-3, 2.7K pull-ups) plus a board-detect line BRD_DT*.
• 1408 Display board (DSP_1408) — ICM7228B decoding HD[00:04] + AS0-2 + WR from the RIO's dedicated 14-pin external display port into eight LTS313A digits (hex/code-B). The board also has a 26-pin "IBM printer port" header with series resistors and per-line LEDs — a diagnostic tap so a PC parallel port can exercise/observe the display bus. Silkscreen reads "P/N 140B" but the schematic title block confirms 1408.
• 1413 Quad Amplifier Board (AMP_PLT, silkscreen "Quad Amplifier Board … P/N 1413 REV. 1") — the actual amplification is a stock Pyramid PB-150P "Pro Plus" 4-channel 12 V car-audio amplifier bolted to the board as a module; the schematic only drew the VWE-designed passive circuitry around it. The board feeds the Pyramid's B+12V / GND / REMOTE screw terminals and speaker-level HIGH INPUT connectors, and its four outputs (1CH/L…4CH/R) return through terminal strips into per-corner 3-way passive crossovers: Dale IHB-3 inductors (820 µH woofer low-pass, 180 µH midrange, date-coded 9531), MMP 100 VDC film capacitors (2.2 µF/10 µF), and Dale CP-5 2 Ω 5 W pad resistors. Corner speaker connectors J1–J4 (front/back × left/right) are 6-pin: 1 woofer+, 2 midrange+, 3 tweeter+, 4 woofer−, 5 midrange−, 6 tweeter− (silkscreen, matching sheet 5). Power enters on J5 (4-pin: +12VDC ×2, GND ×2) with a green POWER ON LED; the per-channel red LED pairs across the outputs are the schematic's "speaker outputs checking circuit". PCB etch NT 1-0A 3695 — the same fab batch series (week 36 '95) as the buttons board.

GAL dump — gal/GAL20v8a_5764.JED

Fuse map read 2023-03-09 from U7 on the 1407 board (GAL20V8A-15LP, hand-labeled "5764" — which matches the JEDEC fuse checksum *C5764, the source of the file name). Per sheet 1 it is the CPU memory decoder (drawn as a 20L8). Decoded — equations, the recovered memory map ($2000-$9FFF SRAM, $A000/$A010/$A020 I/O windows, $C000-$FFFF EPROM) and the firmware cross-check are in gal/README.md; the chip's programmed signature even reads U7.

Schematic scan — schematics/Scans_018-014.pdf

PDF page	Sheet	Title block
1	RIO_1407 sheet 1/3	CPU : Memory Decoder
2	RIO_1407 sheet 2/3	Power & Reset Interface
3	RIO_1407 sheet 3/3	I/O Interface
4	PBE_1401 1/1	Buttons Board
5	AMP_PLT (P/N 1413) 1/1	Amplifier Board
6	KEY_1402 1/1	Keypad Board
7	DSP_1408 1/1	Display Board

Photo index (photos/)

Original Signal filenames preserved here for provenance (all taken 2026-07-15).

File	Original	Shows
encoder-heds5700-control-assembly.jpeg	signal-2026-07-15-093011.jpeg	HP HEDS-5700 I02 encoder (9515 A, Singapore) on a control-mechanism shaft
display-board-1408-front-digits.jpeg	signal-2026-07-15-093017.jpeg	Display board digit side, 8× LTS313A (U2–U9), PCB etch NT 1-0 5094
display-board-1408-back-driver.jpeg	signal-2026-07-15-093023.jpeg	Display board driver side: ICM7228BIPI (date 9438), 16-pin IDC, "RIO EXTERNAL DISPLAY / P/N 140B REV. 1"
keypad-1402-front-keys.jpeg	signal-2026-07-15-093032.jpeg	16-key hex keypad module (keys 0–F), front bezel
keypad-board-1402-back-logic.jpeg	signal-2026-07-15-093038.jpeg	Keypad board logic: DM74LS00N, 2× MM74HCT164N, SN74LS05N, CD74HCT165E, ADR. SEL. jumpers, "P/N 1402 REV. 1"
buttons-board-1401-solder-side.jpeg	signal-2026-07-15-093045.jpeg	Buttons board solder side, PCB etch NT 1-0 3695
buttons-board-1401-component-side.jpeg	signal-2026-07-15-093051.jpeg	Buttons board: 2× CD74HCT165E, 74HCT00AP, 2× UCN5821A-type drivers, 74HCT164N, 8× lamp/button connectors, "P/N 1401 REV. 0"
rio-board-1407-solder-side.jpeg	signal-2026-07-15-093058.jpeg	RIO board solder side, PCB etch NT 3-0 4996
rio-board-1407-component-side.jpeg	signal-2026-07-15-093105.jpeg	RIO board: TMP68HC11 QFP, GAL20V8A ("5764" sticker), AM27C512 EPROM, LH52B256 SRAM, 5× HCTL-2016 + OPT1–5, J11–J18 pod ports, status LEDs, "P/N 1407 REV. 3"

Cross-references

• ../PROTOCOL.md — the 9600 8N1 wire protocol this hardware speaks; its DTR reset pulse and 0x00–0x6F input map both have their physical explanation above.
• ../../rio-firmware/ — v4.2 EPROM dump (from the AM27C512 at U10) and 68HC11 disassembly/patches.
• ../Win32RIO/ — FASA's original Windows driver for the same hardware.