Commit Graph
3 Commits
Author SHA1 Message Date
CydandClaude Opus 5 b615f319db RIO: decode the pod-bus I/O architecture end to end
New IO-ARCHITECTURE.md, derived from the v4.2 image, the U7 GAL decode
and schematic sheets 1/3:

- $A010 control-latch bit map (CCK / D_OUT / WR_SB / RD_SB / SEL0-2)
- the 50-byte script format the firmware replays, and the ROM table map
- full port/address population: 9 buttons boards + 2 keypads across all
  8 ports; the 0x00-0x6F logical map and its 0x48-0x4F gap
- the keypad engine ($CC53/$CC7E): 4-row matrix scan, row-patched RAM
  scripts, the $DC14 key-code table, message type $8B
- lamp readback ($21C2) and the 72-byte lamp-fault mask at $DFA8 --
  fault reports are type $03 with the lamp index in $2519
- scan cycle budget: 1.91 ms/pass, 17.3 ms/scan, ~58 Hz; demux is 60%
- expansion: one spare buttons board, and nothing further without a
  protocol revision

Corrections to existing docs:

- $CC53 was cited as the encoder sweep; it is the keypad-1 scanner.
  The sweep is $C8CC-$C9A7, driven from $C0CB.
- U31 is on sheet 3, not sheet 1, and is completely uncommitted: no
  address, data, strobe or pod-bus signal reaches it. Not an expansion
  hook -- populating it does nothing without new wiring.
- No spare HCTL-2016 footprints exist. The decode has 3 free selects on
  U9, but the PCB carries exactly 5 positions and sheet 1 draws 5.
  More analog axes need hardware, not firmware.

Also carries the previously-uncommitted standard-rate (16550)
feasibility analysis and baudscan.py, plus a note that the FastRIO
"FTDI-class adapter" rule really means arbitrary-rate generation:
CP2102N qualifies, classic CP2102 snaps 31250 to 38400. Bench-measured
2026-07-26; on-cockpit latency check still pending.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-07-26 22:05:29 -05:00
Cyd 26e08a39f7 Fix cross-links in imported RIO docs after the move
Sibling links (hardware<->firmware) now resolve within restoration/;
links to RIOjoy's PROTOCOL.md and Win32RIO/ (which stayed in the RIOjoy
repo) point to gitea web URLs.
2026-07-19 20:48:22 -05:00
Cyd 6bf0ff524d Import RIO board hardware docs from RIOjoy repo (history preserved)
Board photos, scanned schematics, and GAL fuse-map decode of the
physical RIO board set.

git-subtree-dir: restoration/rio-hardware
git-subtree-mainline: def5840e07
git-subtree-split: 42b3944ebe
2026-07-19 20:45:18 -05:00