CydandClaude Fable 5
1323397a50
Predator/IR vision: reverse-engineered from the original firmware and
confirmed by the build team -- it is the Division board's TEXTURE-VALUE RAMP
mode (a "check your texture maps" diagnostic the devs hijacked), NOT a
grayscale squash or a false-colour palette. Located in VREND.MNG (effect
handler @0xe6c0, wire action 0x1b, type -1 ON / -2 OFF); ramp colours from
VR_DRAW.C. Renderer reworked to match: vrview_gl now does the 4-ramp
lerp(color0,color1,luminance(texel)) in the mesh pass (grayscale+defog
removed). Live-rendered on a new night-clear arena egg; crew A/B verdict
pending.
Firmware-decomp toolchain (emulator/firmware-decomp/), all built from the
project's own artifacts and validated:
- coff860.py i860 COFF reader (symbols/sections), names match AS860 source
- derive860.py derives the i860 opcode map from matched .S<->.O pairs
- dis860.py i860 disassembler (98% on clean ground truth; proven on
VREND.MNG -- velocirender_statistics decodes correctly)
- sigmatch860.py reloc-invariant signature matcher onto the stripped image
- i860-encoding.md / FIRMWARE-SYMBOLS.txt / README.md
PVISION-IMPLEMENTATION-GUIDE.md: self-contained hand-off for the BT411 team.
HARDWARE-ARCHITECTURE.md + hardware-photos/ (15 board shots): the Division
VelociRender card is a 2-board stack driving a 3-processor pipeline --
INMOS IMS T425-J25S (comms/control, runs vrendmon.btl) + Intel i860 XP-50 (FP
geometry, runs vrender.mng) + Division PXPL IGC 5.2 ASIC with ~48x PXPL EMC
5.1 (UNC Pixel-Planes-5 SIMD array; "EMC" = the firmware's configEMCs) +
Analog Devices ADV7150 RAMDAC + NTSC. Plus the VWE Video Distribution Board
(P/N 1404: AMD MACH130 + 3x Brooktree Bt477) for the 3-VGA-head cockpit split.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
227 lines
14 KiB
Markdown
227 lines
14 KiB
Markdown
# Division VelociRender card — hardware architecture (for emulation)
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Reconstructed from the firmware (`VREND.MNG`), the DPL3/VRENDER board source, and
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Division's own design docs (`VWE.DOC`, `PXPL5001.DOC`, `CM200IO.H`, `DMA.TXT`).
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**Physical component tables at the bottom are placeholders to fill from the
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photos.** This documents what the software *proves* must be on the board, so the
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photos only need to pin part numbers and quantities.
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## Form factor
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Full-length, full-height, **double-stacked EISA** card pair (operator-described):
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- **Bottom board:** the i860 front-end processor + its DRAM + the host/link
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interface.
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- **Top board:** the **Division PXPL IGC 5.2** rasterizer + supporting logic
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(VRAM, RAMDAC, video out).
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## The pipeline (three stages)
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```
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Host PC (EISA) Card, bottom board Card, top board
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┌───────────────┐ link/CCB ┌────────────────────┐ FIFO/ ┌──────────────────┐
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│ BTL4OPT.EXE │ ─────────► │ i860 front-end │ coeff │ PXPL IGC 5.2 │
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│ VelociRender │ (transputer│ (VREND.MNG): │ stream │ (Pixel-Planes 5) │
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│ wire: draw_ │ link, │ traverse, TRANSFORM│ ─────► │ tiled SIMD │
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│ scene, DCS, │ C011-style│ LIGHT, planarize, │ "down │ rasteriser: │
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│ materials …) │ 0x150) │ binitize, emit │ the │ edge/plane eval, │
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└───────────────┘ │ pxpl5 coefficients │ wire" │ Z-buffer,texture │
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└────────────────────┘ │ → VRAM tiles │
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└───────┬──────────┘
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VRAM→FrameStore│→ RAMDAC → 3 VGA heads
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```
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1. **Host (EISA PC)** runs the game; sends the VelociRender command wire (scene
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graph: create/DCS/draw_scene/materials/effects — *not* transformed geometry).
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2. **i860 front-end** (bottom board, runs `VREND.MNG`): scene traversal,
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per-frame **transform / lighting / planarization / "binitize"**, and
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generation of the per-primitive **coefficient words** the rasterizer consumes.
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Feeds them to the back-end via a FIFO/DMA. (`VWE.DOC`: "push a ton of
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triangles down the wire into the pxpl5 back-end"; a z-buffered flat-shaded
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textured quad = **48 32-bit words**, a triangle ~24.)
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3. **PXPL IGC 5.2 back-end** (top board): Division's implementation of **UNC
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Chapel Hill Pixel-Planes 5** — a *tiled SIMD pixel-processor array*. Per tile
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it evaluates edges/planes, does Z-buffering and texturing, into VRAM tile
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buffers, then VRAM→FrameStore (`DMA.TXT`: tile loop, "wait for 2 interrupts
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from DMA engine (scan-converter + end-of-texture)", `VRAMwritetoFrameStore`).
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4. **Video out:** FrameStore → RAMDAC → **3 VGA heads** (the octopus cable; 5
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mono MFDs + colour radar packed in one framebuffer — see the VDB decode note),
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NTSC timing (`TESTVR.BAT /video NTSC`).
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## Register / command interfaces (what an emulator must model)
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**Host ↔ i860 — transputer link + CCB** (`CM200IO.H`, Division project "BLASTER",
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CM100/CM200 lineage):
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- "860 ↔ transputer io control register", `INPUT_CCB 0xFFFFF000` / `OUTPUT_CCB
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0xFFFFF300` (256-byte Command Control Blocks), `CLEAR_INT`/`INT_CLEARED`.
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- IO opcodes: `IO_LINK_OUT`, `IO_LINK_RAST_OUT`, `IO_DIVNET_IN/OUT/NODE`
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(DIVNET = Division's transputer-link network — this is also the pod-to-pod
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mesh path), `IO_BLOCK_IN/OUT`, `IO_MATHADV_REQ`, `IO_TIMER`.
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- The host side pumps the link via a **C011/C012-style link adapter at EISA I/O
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0x150** (`outveryfast` REP OUTSW); boot resets via port 0x160.
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**i860 → PXPL IGC — coefficient stream** (`DMA.TXT`, `EOF.C` `IGC_*` macros):
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- `IGC_SETENABS`, `IGC_MEMeqSCA_S1`, `IGC_MEMeqZERO`, `IGC_MEMgeSCA_S1`,
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`IGC_CLEAR`, `IGC_CPY`, `send_em(&DMAptr,&coeffptr,…)` — the ops that build the
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per-tile coefficient blocks the IGC executes.
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- IGC per-primitive/per-pixel registers (`dvpx_*`): `dvpx_zbuf`, `dvpx_texid`,
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`dvpx_texsize`, **`dvpx_texmode`**, **`dvpx_texrampsel`** (the material's ramp
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index at the hardware level), `dvpx_diffuse`, `dvpx_specular`, `dvpx_scalar`.
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- **Texture display modes** (`dvpx_eoftexmode`, `EOF.C`): **0 = texture RAMP**
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(texel value → colour ramp — this is where IR/"predator" vision lives; see
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PVISION-IMPLEMENTATION-GUIDE.md), 0x4 = 8-bit mono, 0x6/0x7 = full colour
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(3-3-2 / 4-4-4). The 4 ramps (`texture_ramps[MAX_TEX_RAMPS=4]`) live in IGC
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memory, selected per primitive by `dvpx_texrampsel`.
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## Boot (both processors, every cold start, blind — see board-boot note)
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- **`/tranny vrendmon.btl`** = the **transputer** boot image (INMOS boot-from-
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link; ~85 KB). Loaded first over the link while the transputer is held reset.
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- **`/i860 vrender.mng`** = the **i860** application (~380 KB; disassembles
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cleanly as i860 — confirmed). The renderer logic (incl. pvision) is here.
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- No version handshake possible pre-boot; both are streamed unconditionally.
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## Lineage & external references (for the emulator author)
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- **Division Ltd** (UK), project "BLASTER"; chip generations CM100 → CM200 →
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**PXPL IGC 5.2** (the VWE board).
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- **Rasterizer = UNC Pixel-Planes 5** (Fuchs, Poulton et al., UNC Chapel Hill,
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~1989-92): tiled, SIMD pixel-processor array, "renderer" bin architecture,
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quadratic expression evaluation. Well-documented in the graphics literature —
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the authoritative model for the back-end.
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- **Intel i860 (XR/XP)** front-end — documented ISA; our `dis860.py` disassembler
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reads `VREND.MNG` directly.
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- **INMOS transputer** (T-series) + **C011/C012 link adapters** — documented; the
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host-comms and DIVNET/mesh layer.
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## Emulation implications
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- It's a **3-processor system**: transputer (comms/link/DIVNET), i860
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(geometry/coefficient generation — already disassemblable), PXPL IGC (SIMD
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rasterizer). A bit-exact renderer = run `VREND.MNG` on an i860 core + model the
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IGC's coefficient interpreter (edge/plane eval, Z, texture modes incl. the
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ramp) + the CCB/link glue. The transputer layer can likely be *stubbed* at the
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CCB boundary (as our GL bridge already stubs the link) unless DIVNET/mesh
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behaviour is needed.
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- The IGC is the hard part (custom SIMD ASIC) — but its *programming model* is
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fully visible in `EOF.C`/`PP5REND.C`/the `dvpx_*` set + the PXPL5 docs, and the
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Pixel-Planes 5 literature describes the microarchitecture.
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- Priorities: (1) i860 core + coefficient emit is enough to *drive* a
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functional-accurate rasterizer we write to spec; (2) modeling the IGC exactly
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buys true bit-exactness; (3) transputer only if mesh/DIVNET timing matters.
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---
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## Physical component inventory — IDENTIFIED FROM PHOTOS (2026-07-14, 13 photos)
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Photos in `hardware-photos/` (`01`-`08` close-ups, `09`-`13` the assembly + module
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shots). **Corrected topology (operator + edge-on/separated shots): it is a
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TWO-BOARD stack**, each board covered front and back — the several `DBxxxx`
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silkscreens (all "(C) Division Ltd. 1994") are functional areas/sub-modules of
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the two boards, not separate cards.
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### Board 1 — i860 geometry board (bottom)
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| area | key silicon (as marked) | photos |
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|---|---|---|
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| CPU | **Intel `A80860XP-50`** — i860 **XP, 50 MHz** (heatsinked) | 04, 10-left |
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| coeff FIFO path | **IDT `72510`** FIFOs · grid of Cypress `CY7C451-20` | 04 |
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| working RAM | **2× RAM SIMM** = `DBIO151/03`, **Hitachi `HM624256AJP-25`** DRAM ×6/SIMM | 12-left, 09 |
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| soldered memory | **16× Ramtron `DM2202J-15` EDRAM** | 03, 10-left |
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| I/O / data-mux (other side) | `DBIO152/03` (SN 630254): large `QS74FCT153/158` mux array · Lattice ispLSI 1032/1016 · IDT `16Z646` · `QS338450` bus switches | 01, 11-left |
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| host bus | **gold EISA edge** · IDT `74FCT16292/16841` transceivers ("pma") | 02 |
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| glue/clock | Lattice ispLSI · GAL22V10 · Cypress `CY7B991` RoboClocks | all |
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### Board 2 — PXPL rasterizer board (top)
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| area | key silicon (as marked) | photos |
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|---|---|---|
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| rasterizer control | **`DIVISION PXPL IGC 5.2`** custom ASIC (gold ceramic PGA, date 9447) | 07, 08, 10-right |
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| scan-conversion | **3× Xilinx `XC3090-100`** FPGAs (+ a 4th on the video side) | 07, 08, 10-right |
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| **SIMD pixel array** | **`DBIO153/02` daughter cards: 4 sets of 3 = 12 cards, EACH with 4× `DIVISION PXPL EMC 5.1`** custom chips ⇒ **~48 EMC chips**. (These "look like 12 RAM SIMMs" but are the pixel-plane modules.) Back side: `QS74FCT2821` regd transceivers + `74F08`. | 12-mid/right, 13, 07 |
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| VRAM | ~10-16× Micron `MT42C8256` VRAM | 08, 10-right |
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| RAMDAC | **Analog Devices `ADV7150`** (programmable gamma/palette) | 08 |
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| clocks | ICS `2572` synth · Cypress `CY7B991` | 08 |
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| video out (other side) | `DBE0151 Pixel Planes rev/02` (SN 120227): VGA heads · **Maxim `MAX440/442`** amps · **`LM1882` + `74ACT715` + 14.318 MHz** (NTSC) · Lattice ispLSI 1048 ×2 | 05, 06, 11-right |
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### The big reconciliation: PXPL IGC + PXPL EMC = the rasterizer
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The daughter cards carry **`DIVISION PXPL EMC 5.1`** chips — and **`EMC` is exactly
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the `_configEMCs` / `configEMCs_hi` the firmware programs** (`EOF.C`). So:
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- **`PXPL IGC 5.2`** (1 ASIC on Board 2) = the **I**mage **G**eneration
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**C**ontroller — the master rasterizer that runs the coefficient stream and
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drives the array.
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- **`PXPL EMC 5.1`** (~48 chips on the 12 daughter cards) = the **E**nhanced
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**M**emory **C**ontroller — the **UNC Pixel-Planes-5 SIMD pixel-processor/memory
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array** ("the planes"). Organized 4 banks × 3 cards × 4 chips.
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Together, IGC + EMC array = the complete Division Pixel-Planes 5 rasterizer. The
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texture-mode/ramp work (incl. pvision) is IGC-programmed and executed across the
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EMC array.
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### What the photos pin for emulation
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- **i860 = XP @ 50 MHz** — set the emulated core exactly.
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- **Rasterizer = 1× `PXPL IGC 5.2` + ~48× `PXPL EMC 5.1`** (SIMD array), no public
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datasheet — model from the `dvpx_*`/`IGC_*`/`configEMCs` firmware interface +
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the Pixel-Planes 5 literature. This is the hard part but the programming model
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is fully in-source.
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- **RAMDAC = ADV7150** (documented) — pins the colour/gamma back-end (supersedes
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the guessed `pow(1/1.25)`; read its real config from the firmware).
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- **Video = NTSC** (`LM1882`+`74ACT715`+14.318 MHz, `MAX440/442` amps → VGA heads).
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- **Memory:** i860 = 2× Hitachi-DRAM SIMM + 16× Ramtron `DM2202` EDRAM;
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rasterizer = Micron `MT42C8256` VRAM + the EMC on-chip pixel memory.
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### The transputer — CONFIRMED: INMOS IMS T425-J25S (2026-07-14)
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Firmware proved it first: **`VRENDMON.BTL` is transputer code, not i860** (as i860
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it's garbage; it opens `0xF0`=240 = INMOS **boot-from-link** length byte, then the
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textbook prologue `ajw 4; stl 1; stl 1; stl 1` + coherent `ldl/stnl/ldc/opr`).
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Operator then located the chip on the i860 board (dust-covered, lower-centre-right
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PLCC):
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- **`INMOS IMS T425-J25S`, date 9335 (wk35 1993):** the **32-bit integer
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transputer** — 4 KB on-chip SRAM, 4 serial links, **no FPU** — `J` = 84-pin
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PLCC, `25` = **25 MHz**.
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- The **no-FPU** point confirms the labour split: **T425 = comms/control/boot**
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(runs `vrendmon.btl`; host link + the `CM200IO.H` CCB to the i860 + DIVNET
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pod-mesh over its 4 links, no FP needed); **i860 XP = FP geometry** (runs
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`vrender.mng`). Exactly the 1990 CM200 "860 ↔ transputer" pairing carried into
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the 1994 board.
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- **Emulation impact:** the system is **T425 + i860 XP + IGC/EMC**. `VREND.MNG`
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(i860, disassembles clean via `dis860.py`) and `VRENDMON.BTL` (T425 bytecode)
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are DIFFERENT ISAs — don't run `dis860` on the `.BTL`. For a functional renderer
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the T425 can be stubbed at the CCB/link boundary (as the GL bridge does); for
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bit-exact/timing it must be modelled (INMOS T4-series ISA is well documented —
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the boot image already decodes cleanly).
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## Downstream: the VWE Video Distribution Board (VDB) — photos 14/15
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A **separate board, VWE's own** (not Division): silkscreen **"VIDEO DISTRIBUTION
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BOARD, (C) 1994 V.W.E. Inc., Design by A.G./M.C., P/N 1404 REV.1"**. ISA form
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factor; receives the rendered framebuffer from the Division card and fans it out
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to the cockpit displays — the physical realization of the **3-VGA-head decode**
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(5 mono MFDs + colour radar packed in one 16bpp framebuffer → 3 heads → octopus).
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- **AMD `MACH130-18JC` CPLD** — the pixel routing / region-decode / timing (splits
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the packed framebuffer into per-display regions).
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- **3× Brooktree `Bt477KPJ80`** — 256×24 palette **RAMDACs**, one per VGA head
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(the heads' final DAC is here, distinct from the Division card's `ADV7150`).
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- Support: `74F245`/`74LS125`/`SN74LS541` buffers, `MAD1103` delay lines, an HP
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part, fuse + analog output driver/filter array → D-sub outputs on the bracket.
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- Back = solder-side only, one hand-added **bodge wire** (a Rev.1 fix).
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- **Emulation note:** a display-fanout stage; render-accuracy needs only the
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framebuffer→region mapping (the bridge already models the 3-head split). The
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`Bt477` palettes / `MACH130` matter only for exact per-head colour/timing.
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- **MACH130 "firmware":** no `.JED`/PAL source in the software dump (checked), and
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its FUNCTION is already RE'd in `VDB-NOTES.md` from the MUNGA_L4 driver, so a
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chip dump isn't needed for emulation. It IS **socketed** (84-pin PLCC — easy to
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pull), so a hardware read is possible with a universal programmer that lists
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MACH130 — the only catch is the MACH1xx **security bit** (if set, typical for
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production, readback is blocked). Low priority.
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### Still open (for the hardware owner)
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2. **Exact EMC-array geometry** — confirm 4×3×4 = 48 `PXPL EMC 5.1`, and how the
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4 banks map to screen tiles / the Pixel-Planes bin structure.
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3. **VRAM/EDRAM totals** (count × size) for the frame/Z/texture split.
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4. **`ADV7150` exact variant** + any genlock on the video side.
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