CydandClaude Fable 5
1ceb0dc90f
Operator documented the physical VDB + companion card: Jaton KY2-JAX-CVGA54PCI (Cirrus CL-GD5434) feeds a 26-pin feature-connector ribbon to an AMD/Lattice MACH130-15JC CPLD (the ISA 0x300-0x31A port decoder + hardwired byte-lane splitter), which drives 3x Brooktree Bt477KPJ80 RAMDACs -> one VGA stream to the color radar + a DB25 fan-out to the 5 mono MFDs. Confirms the RE (3 DACs = 3 palette groups; Bt477 6-bit DAC = the driver's shr al,2). A component tied in parallel to the PC front-panel reset (remote reboot or VDB known-state on reset) is under operator research. Also: RP uses the FULL 640x480 on all 6 displays (so our top-strip decode = a framebuffer READ bug, stride/page, not sparse RP content). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
159 lines
8.8 KiB
Markdown
159 lines
8.8 KiB
Markdown
# The VDB — VWE Video Display/Splitter Board
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Reverse-engineered from the shared MUNGA_L4 driver (`CODE/RP/MUNGA_L4/
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L4SVGA16.ASM` + `L4VB16.CPP`/`.HPP`) and the pod emulator's HLE
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(`emulator/vpx-device/vpxlog.cpp`). **A physical VDB sample + its companion
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Cirrus Logic SVGA card exist** (operator, 2026-07-10) — see the hardware
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verification checklist at the end. This board is IDENTICAL between BattleTech
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and Red Planet (shared driver); only the game-side display layout differs.
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## What it is
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An ISA card that **taps the companion Cirrus Logic SVGA card's pixel output**
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off the VGA feature connector and fans that ONE framebuffer out to the six
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secondary cockpit displays (5 mono MFDs + 1 color radar) via three RAMDAC-like
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palette groups. It is a DUMB splitter: no framebuffer of its own, no
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compute — it re-clocks the SVGA pixel stream and routes byte-lanes through
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palette CLUTs to separate VGA heads. "Adam's port decoder design" (Adam G.,
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VWE hardware) per the driver comments.
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The game renders cockpit gauges to the Cirrus SVGA in a **640x480x16bpp**
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mode (VBE mode 0x111; `L4GAUGE=640x480x16`). The Division/VPX card is separate
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(the out-the-window 3D). So the SVGA framebuffer the VDB taps = GAUGES ONLY.
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## Register map (definitive, from L4SVGA16.ASM)
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I/O 0x300-0x31A. Three palette groups, each a 6-bit VGA-DAC-style CLUT. The
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driver's port table (`L4VB16.CPP` ~3685) passes the group base as **base+2**:
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```
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Group base(+2) mask read-addr write-addr data
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NativePalette 0x3C6 (the Cirrus's own VGA DAC — 0x3C6/0x3C8/0x3C9)
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SecondaryPalette 0x302 0x302 0x303 0x304 0x305
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AuxiliaryPal1 0x30A 0x30A 0x30B 0x30C 0x30D
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AuxiliaryPal2 0x312 0x312 0x313 0x314 0x315
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Clock divider: 0x319 write = high-color divider OFF (VWE_HC_OFF)
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0x31A write = high-color divider ON (VWE_HC_ON) (any value)
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```
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Per-group offsets (VGA-DAC layout): **+0 pixel-mask, +1 read-address,
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+2 write-address, +3 data** (auto-incrementing R,G,B triplets). DAC is
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**6-bit**: `SVGAWriteFullPalette` does `shr al,2` (8→6) on write,
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`SVGAReadFullPalette` does `shl al,2` (6→8) on read. Palette load =
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set write-addr to 0, then `rep outsb` 256*3 bytes. Mask write = one `out`
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to base+0. The game only WRITES the VDB (fire-and-forget, no status/ACK);
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reads return DAC read-back.
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## How the split works (the dumb part)
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**High-color clock divider (0x31A on):** in 16bpp mode each pixel is two
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bytes. The divider clocks the LOW byte and HIGH byte of each pixel into
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SEPARATE palette lanes → separate heads. So:
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- **LOW byte (bits 0-7) -> Secondary palette (0x302 group) -> one head**
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- **HIGH byte (bits 8-15) -> Aux1/Aux2 palettes -> the other heads**
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Each head is a physical VGA output off the splitter; an "octopus" cable fans
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the (up to) three head signals to the six cockpit displays. Decode confirmed
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live for BT: radar = low byte via Secondary; the 5 mono MFDs = high byte via
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Aux1/Aux2 color channels. [[vdb-three-vga-head-decode]]
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## How the game packs multiple displays into one framebuffer
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The card is dumb, but the DRIVER is clever about loading the CLUTs so several
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displays share the same pixels. Each cockpit display (`L4GraphicsPort`) has:
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- **`bitMask`** — which framebuffer pixel BITS belong to this display.
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- **`channelEnable`** — which DAC color channel it drives: Red / Green / Blue
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/ AllChannels (+ ...TransparentZero variants that leave index 0 undefined).
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`BuildSecondaryPalette` (low byte = `bitMask & 0xFF`) and
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`BuildAuxiliaryPalette` (high byte = `(bitMask>>8) & 0xFF`) walk the display's
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bits with a `BitWrangler` and write that display's color/ramp into its channel
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of the shared 256-entry CLUT. So N mono displays coexist in one byte-lane by
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owning disjoint bit groups and different color channels; the CLUT decodes each
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combination back to the right per-display brightness. `BuildAuxiliaryPalette`
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generates a linear brightness RAMP across the display's bit values (mono
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MFD = beam intensity); `BuildSecondaryPalette` copies source colors (color
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radar).
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## Palette flash + fade (the pixel-mask cycling)
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`SVGA16::UpdatePalette` (`L4VB16.CPP` ~4196): each palette can FLASH by
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cycling its **pixel-mask** through `mask[]` states at `flashRate` (this is the
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`0x302` mask writes seen cycling e.g. 0x3F/0x7F/0xBF/0xFF — a blink, NOT index
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decode). **Only the Secondary palette is allowed to FADE** (its RGB scaled
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over time). So the pixel-mask register is used as a per-display blink control,
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not (usually) as a decode gate.
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## Our emulation (vpxlog.cpp)
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`vdb_write`/`vdb_read` mirror the register map (`VDB_BASE=0x300`,
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`vdb_group_of`/`vdb_group_base`); `vdb_pal[0/1/2]` = Secondary/Aux1/Aux2.
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`pal_draw` reads the live Cirrus framebuffer (`vga.mem.linear` at
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`vga.config.real_start`, 640x480, stride 1280) and for each pixel looks up
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the low byte via pal0 and high byte via pal1/pal2 (one color channel per mono
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head, pentapus split). 6-bit DAC expanded to 8-bit. `VDB_PALDUMP=<prefix>`
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dumps each group's 768-byte CLUT; pixel-mask writes now log their value; masks
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default 0xFF; `VDB_APPLYMASK=1` ANDs the index with the mask (correct DAC
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emulation, default off = BT-identical).
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## RP vs BT — the OPEN decode problem (2026-07-10)
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Same board, same driver. Captured live for RP (VDB_PALDUMP): framebuffer
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identical (mode 0x111, 640x480); **Secondary/pal0 loads ALL ZEROS** (BT drives
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it as the dynamic color radar) -> our radar head is black; Aux1=green,
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Aux2=RGB are driven; the RP MFD heads decode as SPARSE fragments in the top
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strip. So under the shared mechanism, RP simply puts NO display in the low
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byte (Secondary empty is legitimate), and its high-byte MFD content is not
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landing where our BT-tuned head/channel split expects.
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**Operator's steer: the card is dumb, so the fix is glaringly simple** — not
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a driver-logic difference. Leading suspects to check next (empirically, like
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the first BT pass): (a) the framebuffer PAGE/`real_start` — is RP double-
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buffering so we read a stale/wrong SVGA page? (`SVGASetPage` exists); (b) the
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device DUMP path stopped writing win*.bmp for RP (fires in pal_draw) — worth
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finding why, it may reveal the head-render path isn't running the same;
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(c) which bit groups/channels RP's displays actually claim (dump a BT vs RP
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Aux palette side-by-side; the ramp/channel structure shows the bit layout);
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(d) confirm the low/high byte order and the 640x480 vs a smaller gauge region
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(top-strip content hints RP may draw gauges in fewer rows).
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## Physical hardware (documented from the operator's sample, 2026-07-10)
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CONFIRMS the reverse-engineering below the chip level:
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- **Companion video card**: **Jaton KY2-JAX-CVGA54PCI** — a legacy PCI Local
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Bus VGA card, **Cirrus Logic CL-GD5434** chipset. Renders the cockpit gauges
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(640x480x16, VBE 0x111) and feeds the pixel stream to the VDB via a **26-pin
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ribbon off the VGA Feature Connector**.
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- **The splitter brain**: **AMD/Lattice MACH130-15JC** CPLD — EE-CMOS, 64
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macrocells, 15 ns max prop delay, 84-pin PLCC (2nd-sourced by Rochester
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Electronics). This is "Adam's port decoder": it CONSUMES the feature-connector
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video stream AND takes instructions from the **ISA bus** (the 0x300-0x31A
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register file — palette loads, masks, and the 0x319/0x31A high-color clock
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divider). It does the byte-lane split in hardwired logic (same for BT and RP).
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- **The three DACs**: **3x Brooktree Bt477KPJ80** RAMDACs (256-entry, 6-bit/
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channel, 80 MHz) = the three palette groups Secondary/Aux1/Aux2. The Bt477's
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6-bit DAC is exactly why the driver does `shr al,2` (8->6) on palette writes.
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Output routing (confirms the head map): **one Bt477 -> a VGA stream to the
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color RADAR display** (= Secondary/0x302); the **other two Bt477s -> a DB25
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connector that fans out to the 5 monochrome MFDs** (= Aux1/0x30A R,G = 2
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lower MFDs, Aux2/0x312 R,G,B = 3 upper MFDs; 5 mono wires total, one channel
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unused). The DB25 fan-out is the "octopus/pentapus" cable.
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- **Reset-tie component**: a part wired in PARALLEL with the PC's front-panel
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RESET switch — either a remote-reboot path OR a means to force the VDB into
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a known state when the PC is reset (so the CPLD/DACs re-init cleanly).
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OPERATOR RESEARCHING. (Plausible: the CPLD needs a hard reset synchronized
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with the host, since it has no software reset in the 0x300-0x31A map -- only
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clock on/off; a reset tie guarantees the splitter isn't left mid-state.)
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### Still worth capturing for the archive
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- Photos of each chip + the board silkscreen; the DB25 pinout (which pin ->
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which MFD) and the 26-pin feature-connector ribbon pinout.
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- Whether the MACH130 JEDEC fuse-map is readable (a MACH130 can often be
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read back unless secured) -- that IS the splitter logic, the ultimate
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ground truth, and preservable like the RIO EPROM.
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- The reset-tie circuit trace (operator's follow-up).
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Related: [[vdb-three-vga-head-decode]], [[tesla-cockpit-emulator-state]].
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