CydandClaude Fable 5
1fecd7e274
New --mash mode (tools/RioSerialMonitor/MashTest.cs) mechanizes the wedge-patch validation plan from RIOv4_2-ANALYSIS.md: - Runs the live link with the app's >5s reset-recovery DISABLED so a board wedge stays observable, and echoes lamps on every press (lamp/reply collisions are the wedge trigger). - Gap timing uses ANY AnalogReply packet (0xFE sentinels included - a sentinel still proves the reply path is alive); logs a gap histogram + top-10 longest gaps with timestamps. - WEDGE detector: analog silent past the threshold (default 2s) -> beep + banner; on resume, classifies self-recovered (patched expectation) vs button-revived (button event within 300ms of resume, the unpatched signature) vs unresolved at run end. - Board self-reported RestartCount/AbandonCount/FullBufferCount snapshotted before/after via CheckRequest, delta printed (7-bit wrap-aware). - Fixed-layout summary teed to riomash-<label>-<stamp>.log so baseline-vs-patched runs diff directly. Exit 0 = no wedge, 1 = wedge. --mash --selftest drives the whole instrument against a scripted in-memory board (SelftestTransport) that goes silent at t=4.0s and revives 200ms after a button at t=6.5s: verified end-to-end - alarm at 6.0s, wedge classified button-revived (2.75s), counter delta +4/+0/+1, verdict FAIL, exit 1. Use it to sanity-check the alarm at the cabinet. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
RIO board firmware
RIOv4_2.bin— RIO cockpit I/O board firmware v4.2, dumped 2026-07-04 from one of our own boards' EPROM: an AMD AM27C512-150 (64K x 8 UV EPROM, 150ns — the image fills it exactly). sha25660a88718835c654b6135dbec7721c40ef99dca07df2ad4b57eedeb24037a5f73. For the eventual patched burn: a pin-compatible Winbond W27C512 (electrically erasable, TL866-friendly) drops straight into the socket; the original AMD chip gets labeled and preserved unmodified.
First-look analysis (from the image alone, confirmed on hardware)
- MCU: Toshiba TMP68HC11 (read off the chip; the code fingerprint
agrees — 6800-family opcodes with writes into the 68HC11 internal
register block at
$10xx). - Memory map: image is FF up to 0xC000; 16KB of code occupies
$C000-$FFFF(EPROM mapped at the top of the HC11 address space). - Startup at
$C000:SEI; LDS #$8000; STAA $1024 (TMSK2); STAA $1022 (TMSK1); ...then a longJSRinit chain — textbook HC11 bring-up. - Vector table (
$FFD6-$FFFF, big-endian):$FFFERESET →$C000$FFD6SCI (serial) →$D630— the entry point of the board's receive/protocol interrupt handler. The suspected board-side DISABLE_AND_DIE-style wedge (see RIO-NOTES.md: the board mirrors the game's PCSPAK state machine, and mash-stress leaves the reply path dead while the button/event path stays alive) is reachable from here.$FFE4→$C1B2,$FFE6→$C18E(timer output-compares); most other vectors →$DB07..$DB3Dstubs.
Why this exists
The remaining RIO reliability issue is board-side: under button-mash
stress the board's reply/analog state machine wedges (RX dead, TX alive;
a button press or power cycle revives it), reproduced identically on two
different USB serial adapters. The game-side half of the protocol was
binary-patched for tolerance (BTL4OPT patches v2-v4); the board firmware
is the other half. Plan (RIO-NOTES.md "Board firmware patch plan"):
disassemble as 68HC11 from $C000 with the vector entries as roots, find
the SCI state machine (protocol constants FC=ACK FD=NAK FE=RESTART
FF=IDLE, idle-reload-4 patterns), patch the early-ACK/error wedge path or
widen its window, burn a new EPROM, keep this original safe.