CydandClaude Fable 5
2f5fc505d6
New display-board-1408.md: pin-level definition of the board's outputs (8 multiplexed hex digits via ICM7228B, isolated LPT LED monitor block, no readback path) and, from the firmware disassembly, everything the RIO puts on it: F0 boot banner, F1 test-mode banner (keypad sequence A-9-E enters, D exits), and the sub-test displays — five live encoder-count readouts, button test with input index, two lamp patterns, keypad test. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
171 lines
11 KiB
Markdown
171 lines
11 KiB
Markdown
# RIO cockpit hardware — boards, schematics, GAL dump
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Physical documentation of the VWE Tesla-cockpit **RIO** (Remote Input/Output)
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board set, gathered during the 2026 restoration: board photos (Signal,
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2026-07-15), a scan of the original paper wire schematics, and the fuse map
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read out of the RIO board's GAL address decoder.
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All boards are **Copyright 1994 V.W.E. Inc.** — the schematic title blocks
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spell it out: **Virtual World Entertainment, 1100 W Cermak Suite B404,
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Chicago, Illinois**, every sheet and silkscreen credited **"Design by M.C."**
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Schematic plots are dated 1/11/1996 (peripheral boards) and 6/26/1996 (RIO
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board), so these drawings post-date the Rev. 0/1 boards they describe.
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## Board family
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| P/N | Title | Rev photographed | Key silicon |
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|-----|-------|------------------|-------------|
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| **1407** | RIO board ("CPU board") | Rev. 3 | Toshiba **TMP68HC11** @ 8 MHz, GAL20V8A decoder, 27C512 EPROM, LH52B256 32K SRAM, 5× HCTL-2016 |
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| **1401** | Buttons board | Rev. 0 | 2× UCN5821A lamp drivers, 2× 74HCT165, 74HCT164, 74LS00/05 |
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| **1402** | Keypad board | Rev. 1 | 2× 74HCT164, CD74HCT165, 74LS00/05 |
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| **1408** | Display board ("RIO external display") | Rev. 1 | Intersil **ICM7228B** 8-digit driver, 8× LTS313A 7-segment |
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| **1413** | Quad Amplifier Board | Rev. 1 | **Pyramid PB-150P "Pro Plus"** car amp (bolt-on) + passive 3-way crossovers |
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Plus the cockpit position sensors: **HP HEDS-5700** two-channel quadrature
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optical encoders (option code **I** = 512 counts/rev; the photographed unit is
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date-coded 9515, Singapore), one per analog axis, read by the five HCTL-2016
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counters on the RIO board (`OPT1`–`OPT5` = stick X/Y, throttle, left/right
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pedals).
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## RIO board 1407 (schematic sheets 1–3, `RIO_1407`)
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**Sheet 1 — CPU : Memory Decoder.** The TMP68HC11 runs in expanded
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multiplexed mode: a 74HCT573 latches A[0:7] off the AD bus, and **U7 — drawn
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as a 20L8, fitted as a GAL20V8A-15LP** — decodes A[8:15] into `ROM_SEL*`
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(27C512 EPROM, U10), `RAM_SEL*` (LH52B256-70LL 32K SRAM, U11), `PH_SEL*`
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(HCTL-2016 bank via two 74LS138s), `DSP_SEL*` (external display port) and
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`BND_SEL` (I/O-interface latch, sheet 3). Each HCTL-2016 feeds a 5-pin
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header (`J4`–`J8`) carrying CHA/CHB from a HEDS-5700. The DB9 COM port goes
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through a MAX231/MAX232-class level shifter; the schematic's `IN_RESET*` from
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the serial side is the hardware behind the **DTR reset pulse** described in
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[PROTOCOL.md](../PROTOCOL.md) §1. The "display interface" block (ALS541
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buffers, HEADER14) exports latched data lines `HD[00:04]` + digit address
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`AS0-2` to the display board — this is a memory-mapped port, *not* the pod
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bus. A 22V10 site (U31) is drawn mostly N/C and is **unpopulated** on the
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photographed board.
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**Sheet 2 — Power & Reset Interface.** A MAX690 supervisor provides
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power-fail reset and a **watchdog (WDI)**; reset can also come from the
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front-panel `RESET` toggle (SW1) or remotely through an **H11L1 optocoupler**
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fed from an isolated 3-pin `+5 VDC` input (J8) — the game PC can hard-reset
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the board. The `ABORT` toggle (SW2) pulls the HC11 `IRQ*`. A 74LS241 drives
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the status LED bank: `POWER ON`, `FAULT`, `RESET`, `RUN`, `TX`, `RX`. Power
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enters on J9 through 5 A/10 A fuses, LC filters and 1N5341B clamp zeners,
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producing separate logic `VCC` and peripheral `VCC_EXT` rails.
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**Sheet 3 — I/O Interface ("pod bus").** Eight identical 16-pin IDC ports
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(`J11`–`J18`) fan out through ALS541 buffers and SIP resistor packs. All
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ports share the outbound signals; each port has its own return line
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(`DI[0..7]`, selected by a 74LS138 from `SEL0-2`) and its own buffered
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brightness line (`BRT_CTR0-7`, all copies of one PWM signal). A 74HC574
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latch written via `BND_SEL` holds the bus control bits (`SEL0-2`, `RD_SB`,
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`WR_SB`, `D_OUT`, `CCK`) — so the firmware bit-bangs the bus by rewriting
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this latch.
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### Pod bus signal set (per port)
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| Signal | Direction | Purpose |
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|--------|-----------|---------|
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| `CCK` | RIO → pod | shift clock |
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| `DD_IN` | RIO → pod | serial data into the pod's 74HCT164s (address select + payload) |
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| `WR_SB` | RIO → pod | write strobe (latch lamp/display data) |
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| `RD_SB` | RIO → pod | read strobe (parallel-load the pod's 74HCT165) |
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| `DD_OUT` | pod → RIO | serial readback, **open-collector 74LS05** so pods can share a cable |
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| `BRT_CTR` | RIO → pod | global lamp-brightness PWM, gates the UCN5821A output enable |
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| `VCC_EXT`, GND | — | peripheral power rail |
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Every pod board carries a 74HCT164 whose parallel outputs go to an
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**`ADR. SEL.` jumper block (`A-0`…`A-7`)**: the RIO shifts an address
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pattern down the cable, the jumper picks which bit this board answers to,
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and 74LS00 gates qualify `RD_SB`/`WR_SB` with that selection. This
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hardware addressing is what the 0x00–0x6F logical input map in
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[PROTOCOL.md](../PROTOCOL.md) ultimately resolves to.
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## Peripheral boards
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- **1401 Buttons board** (`PBE_1401`) — eight 4-pin connectors (`J3`–`J10`),
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pinout `1 = buttons GND, 2 = button in, 3 = lamps +5V, 4 = lamps logic GND`.
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Two UCN5821A serial-in latched sink drivers light the button lamps
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(brightness = `BRT_CTR` PWM on their OE), two 74HCT165s read the buttons
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back, one of them also echoing board status/address.
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- **1402 Keypad board** (`KEY_1402`) — hosts the COTS 16-key hex pad (0–F)
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on an 8-line header (4×4 matrix). A second 74HCT164 drives the matrix
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rows through open-collector 74LS05 inverters; the 74HCT165 reads the four
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columns (`IN0-3`, 2.7K pull-ups) plus a board-detect line `BRD_DT*`.
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- **1408 Display board** (`DSP_1408`) — ICM7228B driving eight LTS313A
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digits (hex decode) from the RIO's dedicated 14-pin *external display*
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port; write-only, plus an isolated 26-pin **"IBM printer port"** LED
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monitor block. Silkscreen reads "P/N 140B" but the schematic title block
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confirms **1408**. Full pin-level output definition — and what the
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firmware actually displays (boot banner + the keypad-A-9-E test mode) —
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in [display-board-1408.md](display-board-1408.md).
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- **1413 Quad Amplifier Board** (`AMP_PLT`, silkscreen "Quad Amplifier
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Board … P/N 1413 REV. 1") — the actual amplification is a stock
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**Pyramid PB-150P "Pro Plus"** 4-channel 12 V car-audio amplifier bolted
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to the board as a module; the schematic only drew the VWE-designed
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passive circuitry around it. The board feeds the Pyramid's `B+12V / GND
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/ REMOTE` screw terminals and speaker-level `HIGH INPUT` connectors, and
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its four outputs (`1CH/L`…`4CH/R`) return through terminal strips into
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per-corner 3-way passive crossovers: Dale IHB-3 inductors (820 µH woofer
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low-pass, 180 µH midrange, date-coded 9531), MMP 100 VDC film capacitors
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(2.2 µF/10 µF), and Dale CP-5 2 Ω 5 W pad resistors. Corner speaker
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connectors J1–J4 (front/back × left/right) are 6-pin: `1 woofer+,
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2 midrange+, 3 tweeter+, 4 woofer−, 5 midrange−, 6 tweeter−` (silkscreen,
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matching sheet 5). Power enters on J5 (4-pin: `+12VDC ×2, GND ×2`) with a
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green POWER ON LED; the per-channel red LED pairs across the outputs are
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the schematic's "speaker outputs checking circuit". PCB etch NT 1-0A 3695
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— the same fab batch series (week 36 '95) as the buttons board.
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## GAL dump — [`gal/GAL20v8a_5764.JED`](gal/GAL20v8a_5764.JED)
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Fuse map read 2023-03-09 from **U7 on the 1407 board** (GAL20V8A-15LP,
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hand-labeled **"5764"** — which matches the JEDEC fuse checksum `*C5764`, the
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source of the file name). Per sheet 1 it is the CPU **memory decoder**
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(drawn as a 20L8). **Decoded** — equations, the recovered memory map
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(`$2000-$9FFF` SRAM, `$A000/$A010/$A020` I/O windows, `$C000-$FFFF` EPROM)
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and the firmware cross-check are in [`gal/README.md`](gal/README.md); the
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chip's programmed signature even reads `U7`.
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## Schematic scan — [`schematics/Scans_018-014.pdf`](schematics/Scans_018-014.pdf)
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| PDF page | Sheet | Title block |
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|----------|-------|-------------|
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| 1 | RIO_1407 sheet 1/3 | CPU : Memory Decoder |
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| 2 | RIO_1407 sheet 2/3 | Power & Reset Interface |
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| 3 | RIO_1407 sheet 3/3 | I/O Interface |
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| 4 | PBE_1401 1/1 | Buttons Board |
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| 5 | AMP_PLT (P/N 1413) 1/1 | Amplifier Board |
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| 6 | KEY_1402 1/1 | Keypad Board |
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| 7 | DSP_1408 1/1 | Display Board |
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## Photo index ([`photos/`](photos/))
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Original Signal filenames preserved here for provenance (taken 2026-07-15;
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amplifier board 2026-07-19).
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| File | Original | Shows |
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|------|----------|-------|
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| `encoder-heds5700-control-assembly.jpeg` | `signal-2026-07-15-093011.jpeg` | HP HEDS-5700 I02 encoder (9515 A, Singapore) on a control-mechanism shaft |
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| `display-board-1408-front-digits.jpeg` | `signal-2026-07-15-093017.jpeg` | Display board digit side, 8× LTS313A (U2–U9), PCB etch NT 1-0 5094 |
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| `display-board-1408-back-driver.jpeg` | `signal-2026-07-15-093023.jpeg` | Display board driver side: ICM7228BIPI (date 9438), 16-pin IDC, "RIO EXTERNAL DISPLAY / P/N 140B REV. 1" |
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| `keypad-1402-front-keys.jpeg` | `signal-2026-07-15-093032.jpeg` | 16-key hex keypad module (keys 0–F), front bezel |
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| `keypad-board-1402-back-logic.jpeg` | `signal-2026-07-15-093038.jpeg` | Keypad board logic: DM74LS00N, 2× MM74HCT164N, SN74LS05N, CD74HCT165E, ADR. SEL. jumpers, "P/N 1402 REV. 1" |
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| `buttons-board-1401-solder-side.jpeg` | `signal-2026-07-15-093045.jpeg` | Buttons board solder side, PCB etch NT 1-0 3695 |
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| `buttons-board-1401-component-side.jpeg` | `signal-2026-07-15-093051.jpeg` | Buttons board: 2× CD74HCT165E, 74HCT00AP, 2× UCN5821A-type drivers, 74HCT164N, 8× lamp/button connectors, "P/N 1401 REV. 0" |
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| `rio-board-1407-solder-side.jpeg` | `signal-2026-07-15-093058.jpeg` | RIO board solder side, PCB etch NT 3-0 4996 |
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| `rio-board-1407-component-side.jpeg` | `signal-2026-07-15-093105.jpeg` | RIO board: TMP68HC11 QFP, GAL20V8A ("5764" sticker), AM27C512 EPROM, LH52B256 SRAM, 5× HCTL-2016 + OPT1–5, J11–J18 pod ports, status LEDs, "P/N 1407 REV. 3" |
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| `amp-board-1413-component-side.jpeg` | `signal-2026-07-19-134932.jpeg` | Quad Amplifier Board full view: Pyramid PB-150P module, corner crossovers, "P/N 1413 REV. 1", J5 pinout silkscreen |
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| `amp-board-1413-solder-side.jpeg` | `signal-2026-07-19-134926.jpeg` | Amplifier board solder side, PCB etch NT 1-0A 3695 |
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| `amp-board-1413-pyramid-inputs.jpeg` | `signal-2026-07-19-134921.jpeg` | Pyramid input face: HIGH INPUT connectors, LEVEL pots, LOW INPUT RCAs; front-corner crossovers |
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| `amp-board-1413-pyramid-outputs.jpeg` | `signal-2026-07-19-134915.jpeg` | Pyramid output face: SPEAKERS terminals 1CH/L–4CH/R, blade FUSE, B+12V/GND/REMOTE; check LEDs, J1–J4 pinout silkscreen |
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## Cross-references
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- [`../PROTOCOL.md`](../PROTOCOL.md) — the 9600 8N1 wire protocol this
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hardware speaks; its DTR reset pulse and 0x00–0x6F input map both have
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their physical explanation above.
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- [`../../rio-firmware/`](../../rio-firmware/) — v4.2 EPROM dump (from the
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AM27C512 at U10) and 68HC11 disassembly/patches.
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- [`../Win32RIO/`](../Win32RIO/) — FASA's original Windows driver for the
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same hardware.
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