CydandClaude Opus 4.8
ba7c657dd9
The governing insight: specification is the bottleneck, not substrate -- igc_exec.py is the golden reference model every port (RTL or GPU) validates against. EMC array = natural FPGA target (208KB BRAM + ~50k LUT full-parallel, or 8:1 muxed); IGC = reimplementation from our cracked ISA; i860 = software (emu860 as executable spec); wire-identical boot via the blind boot-from-link property. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
98 lines
5.1 KiB
Markdown
98 lines
5.1 KiB
Markdown
# Reconstructing the VelociRender in hardware — FPGA design note (2026-07-19)
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Companion to HARDWARE-ARCHITECTURE.md and IGC-ENCODING-DERIVATION.md. Scope:
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what a faithful FPGA reconstruction of the Division VelociRender (double-stacked
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EISA, T425 + i860 XP + PXPL IGC 5.2 + EMC array) would take, what already
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exists, and how the current software work feeds it.
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## The governing insight
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The bottleneck is **specification, not substrate**. The IGC/EMC behaviour we
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are still deriving (the last eof opcodes, the TXDN texture-fetch protocol) is
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required identically by an RTL build — you cannot synthesize what you cannot
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specify. `igc_exec.py` is therefore built as the **golden reference model**:
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any RTL (or GPU) port validates frame-for-frame against it, and it validates
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against the real firmware's captured streams.
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## The beautiful property: wire-identical boot
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The board is blind-loaded every cold boot — the transputer streams
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VRENDMON.BTL + VREND.MNG down the link with **no version check** (see
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board-boot notes). A reconstructed card that implements the link + CCB
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handshake accepts the *real firmware from the real host software* and is
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indistinguishable on the wire. The whole wire protocol is known
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(VELOCIRENDER_PROTOCOL.md); the boot handshake is implemented in our emulator.
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## Block-by-block
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### EMC array — the natural FPGA target
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- Per tile: 64×128 = 8,192 PEs, 208 bits pixel memory each (PXPL5002.DOC bit
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allocations; DIVPXMAP.H field map), 1-bit enable, shared linear-expression
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tree (eval = int(Ax+By+C) per pixel), bit-serial ALU (~2 bits/clock per the
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len+115 cycle counts in the instruction words).
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- FPGA budget (one tile, fully parallel): 8,192 × 26B = **208 KB pixel RAM**
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(~52 BRAM36) + 8,192 serial ALUs (~5-8 LUT each ≈ 40-65k LUT) + the tree
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evaluator (DSP adders). Fits a mid-range part (Artix-7 100T tight,
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Kintex/UltraScale+ comfortable). Time-multiplexing 8:1 makes it tiny — the
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original ran ~40 MHz; 200 MHz fabric has 5× headroom before parallelism.
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- The original processed the frame's 52 tiles (832×512 / 64×128) sequentially
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per renderer — an FPGA build does the same with one physical tile.
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### IGC sequencer — reimplementation from our ISA spec
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- Custom UNC Pixel-Planes 5-lineage silicon. No netlist, no HDL, no docs in
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the dump. The instruction set is the one we cracked:
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`addr | op<<8 | aux<<16 | (len+115)<<23 | S1<<31`, op table in
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IGC-ENCODING-DERIVATION.md (named via ADDR + DUMP + expanded compiler
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output). An RTL IGC = a decoder + micro-sequencer driving the EMC controls —
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straightforward ONCE the op table is complete. **Open items = the same
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spec gaps the emulator has** (a handful of eof ops, SCMEMA/FCMEMA seed
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semantics, carry/latch details).
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### DMA engine
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- Descriptor format fully known (DMAENGN.H + live captures): 64-bit
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{addr, count|opcode} pairs, SEND/SENDE/TILE/TXDN/GOTO/FLUSH/WAIT/STOP,
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127-longword chunking, GOTO-chained binchunks. Trivial RTL.
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- **Open item: the TXDN texture-fetch path** (texels stream to the EMC io
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port, bits 24+, via nested download programs at 0x8018000+) — being mapped
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now; needed by every substrate.
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### i860 XP — the mountain, and how to route around it
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- No mature open i860 core known to us (fact-check welcome). The chip's
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exposed pipelines (3-stage FP adder, 2/3-stage multiplier, KR/KI/T, DIM,
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delay-slot annulment) are exactly what we had to model in emu860 — which is
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now MAME-validated + capture-validated and constitutes an executable spec
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for any future RTL attempt.
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- Pragmatic architecture: **i860 in software** — a C/JIT port of emu860 (the
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original is ~40 MHz dual-issue; a modern host or a Zynq hard-core reaches
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real-time comfortably), feeding the FPGA raster side through the same DMA
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queue interface the real firmware uses. i860 RTL is a separate multi-month
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project nobody needs for either goal.
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### T425 transputer
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- Open T4xx cores exist; but the transputer is boot/comms only. For a
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wire-identical card, implement the link + iserver handshake + CCB mailbox
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(all documented/emulated already) — a small FSM, not necessarily a full
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transputer.
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### Video out
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- 832×512 native (dPL3), ADV7150 DAC on the original; standard timing + the
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ramp/texmode LUT stage (output colour = ramp(texu) — pvision model). The
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ramp tables come over the wire; the LUT is a BRAM.
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## Three retargets of one spec
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| Goal | Substrate | Note |
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| DOSBox renderer (ship as software) | **GPU compute** | EMC pixel = GPU thread; 1:1 mapping; real-time trivial |
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| Physical pod card / preservation | **FPGA raster + software i860** | wire-identical boot; EISA/link adapter |
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| The spec itself | `igc_exec.py` (now) | golden model both validate against |
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## Sequencing
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1. Finish the spec (TXDN protocol, last ops) in the emulator — in progress.
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2. Restructure `igc_exec` so the op table + tile semantics are a clean,
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portable core (parser / semantics / readout separated).
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3. First retarget: GPU compute for the DOSBox goal (smallest step, biggest
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payoff for the project's stated aim).
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4. FPGA raster side when/if a physical build is wanted — this note is its
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starting brief.
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