CydandClaude Fable 5
df5804e835
make_patch.py gains --baud31250: one byte beyond the wedge patch — the SCI init operand at $D62B ($30 -> $02). BAUD $30 = /13 prescale, /1 divider (2MHz E / 208 = 9615); $02 = /1, /4 -> 31250 exactly, 3.3x faster. The init write also confirms the 8MHz crystal, which is why 19200/38400 are unreachable and why 62500/125k are left alone pending an ISR cycle count. - 24 bytes changed vs original (sha256 9f866cf3...); re-disassembly diff vs the classic patched image shows exactly the one operand line, and the classic build still reproduces 3fc8170c... (script regression-safe). - PC side: SerialPortTransport takes an optional baudRate (default 9600, runtime untouched); RioSerialMonitor + --mash accept --baud 31250. - Caveats documented in README/ANALYSIS: non-standard rate (FTDI-class adapters only, no 16550s); native games still speak 9600 so this chip is bench/RIOJoy-only; validate the wedge patch at 9600 first. 275 tests green; mash --selftest regression unchanged (FAIL/exit-1). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
53 lines
2.8 KiB
Markdown
53 lines
2.8 KiB
Markdown
# RIO board firmware
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- **`RIOv4_2.bin`** — RIO cockpit I/O board firmware **v4.2**, dumped
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2026-07-04 from one of our own boards' EPROM: an **AMD AM27C512-150**
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(64K x 8 UV EPROM, 150ns — the image fills it exactly).
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sha256 `60a88718835c654b6135dbec7721c40ef99dca07df2ad4b57eedeb24037a5f73`.
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For the eventual patched burn: a pin-compatible Winbond W27C512
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(electrically erasable, TL866-friendly) drops straight into the socket;
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the original AMD chip gets labeled and preserved unmodified.
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## First-look analysis (from the image alone, confirmed on hardware)
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- MCU: **Toshiba TMP68HC11** (read off the chip; the code fingerprint
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agrees — 6800-family opcodes with writes into the 68HC11 internal
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register block at `$10xx`).
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- Memory map: image is FF up to **0xC000**; 16KB of code occupies
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`$C000-$FFFF` (EPROM mapped at the top of the HC11 address space).
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- Startup at `$C000`: `SEI; LDS #$8000; STAA $1024 (TMSK2);
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STAA $1022 (TMSK1); ...` then a long `JSR` init chain — textbook HC11
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bring-up.
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- Vector table (`$FFD6-$FFFF`, big-endian):
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- `$FFFE` RESET → `$C000`
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- **`$FFD6` SCI (serial) → `$D630`** — the entry point of the board's
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receive/protocol interrupt handler. The suspected board-side
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DISABLE_AND_DIE-style wedge (see RIO-NOTES.md: the board mirrors the
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game's PCSPAK state machine, and mash-stress leaves the reply path
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dead while the button/event path stays alive) is reachable from here.
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- `$FFE4` → `$C1B2`, `$FFE6` → `$C18E` (timer output-compares); most
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other vectors → `$DB07..$DB3D` stubs.
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## Why this exists
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The remaining RIO reliability issue is board-side: under button-mash
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stress the board's reply/analog state machine wedges (RX dead, TX alive;
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a button press or power cycle revives it), reproduced identically on two
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different USB serial adapters. The game-side half of the protocol was
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binary-patched for tolerance (BTL4OPT patches v2-v4); the board firmware
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is the other half. Plan (RIO-NOTES.md "Board firmware patch plan"):
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disassemble as 68HC11 from `$C000` with the vector entries as roots, find
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the SCI state machine (protocol constants FC=ACK FD=NAK FE=RESTART
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FF=IDLE, idle-reload-4 patterns), patch the early-ACK/error wedge path or
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widen its window, burn a new EPROM, keep this original safe.
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## Patched images (built by make_patch.py; see RIOv4_2-ANALYSIS.md)
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- **`RIOv4_2_patched.bin`** — the reply-latch wedge fix, 23 bytes changed.
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sha256 `3fc8170caf60e2580641724ff995176c93c4f2e706f31487beded8233142493f`.
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- **`RIOv4_2_patched_31250.bin`** (`make_patch.py --baud31250`) — wedge fix
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+ SCI retuned 9600 → 31250 baud (one more byte, `$D62B: 30→02`).
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sha256 `9f866cf353d04906e1d3e3847b6375eaae251c987b656f68f093e61ba1bd545b`.
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Bench/RIOJoy-only until the native games get baud patches; needs an
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FTDI-class adapter (16550s can't make 31250). Test tools take `--baud 31250`.
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