CydandClaude Opus 4.8
5d29442ecb
igc_conformance.py pins the reference behaviour any port (RTL/GPU/C) must reproduce: the DUMP packet parse, a synthetic raster, the bars pipeline (texu==x+2 from the real cap7 tile programs), and the fxtest effect primitives (coverage + z pinned) -- fixtures committed under conformance/. GPU-RETARGET.md maps the DOSBox-renderer path: EMC tile as compute shader (pixel=thread), 4 milestones, conformance-gated. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
71 lines
3.3 KiB
Markdown
71 lines
3.3 KiB
Markdown
# GPU-compute retarget — the DOSBox-renderer path (2026-07-19)
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Companion to FPGA-RECONSTRUCTION.md. This is the plan for shipping the decoded
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IGC/EMC model as a real-time renderer behind the existing DOSBox seam — the
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practical answer to "use this as the renderer for the pod."
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## Why GPU compute
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The EMC array is 8,192 bit-serial PEs per 64×128 tile. On a GPU that is one
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thread per pixel executing the same decoded op stream — a literal 1:1 mapping,
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no hardware, ships as software next to the renderer we already deploy.
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The original array ran ~40 MHz bit-serial; any integrated GPU exceeds the
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whole frame's work by orders of magnitude.
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## Architecture
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```
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DOSBox (game, unmodified)
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│ wire protocol (known) ── existing seam: render-bridge/live_bridge
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▼
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emu860 geometry stage ── the i860 firmware, C/JIT port for realtime
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│ per-draw DMA stream + payloads (the coefficient programs)
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▼
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IGC translator (host) ── igc_exec.parse -> flat op records
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│ SSBO: op stream + payload floats + tile list
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▼
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compute shader "EMC tile" ── pixel = thread; fields in registers/LDS:
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│ texz/texu/texv/zbuf as uint20, r/g/b as uint8, enable as bool;
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│ ops = a switch over the named table (TREE*, MEM*, CPY, sweeps, SCA*)
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▼
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readout pass ── ramp(texu) / rgb24 -> RGBA8 frame texture
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▼
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present (the existing renderer window / vr_readpixels reply)
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```
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## What ports 1:1 from the golden model
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- The op table (data) and parser — host-side, unchanged.
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- Tile semantics — each `Tile.run` branch becomes a shader case; the pixel
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memory bit-fields become packed uints (no bit-serial emulation needed:
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field-level semantics are already proven equivalent by the conformance
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suite).
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- Readout — ramp LUT as a small texture.
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## Conformance gate
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`igc_conformance.py` (C1-C4, committed fixtures) is the acceptance bar: the
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shader path must reproduce C2-C4 outputs exactly (C1 is host-side parse).
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Add a C5 full-frame image hash (bars + fxtest frames) once texel sampling
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lands.
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## Realtime budget (per frame)
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- 52 tiles × ~100-3000 op-steps × 8,192 px ≈ 1-10 G pixel-ops worst case —
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a compute-shader trifle at 60 fps on integrated graphics.
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- Geometry stage: the real wall. emu860 in Python ≈ 600K steps/s; a frame is
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~10-50M steps → need the C/JIT step-core (planned; the i860 ISA semantics
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are fully pinned by emu860 + MAME cross-validation). Interim: pre-captured
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streams replay at full speed for validation.
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## Milestones
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1. **M1 shader tile**: WGPU/GL compute kernel executing the named ops;
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passes C2-C4. (small)
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2. **M2 frame loop**: DMA-stream walker + tile dispatch + readout; renders
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the bars + fxtest fixtures. (small-medium)
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3. **M3 texel path**: TXDN stream -> texture sampling (needs the remaining
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spec work — the io-port fetch protocol). (medium, spec-gated)
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4. **M4 live seam**: behind live_bridge in place of / beside the GL renderer;
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real-time gate = the C step-core for emu860. (the big one, independent)
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## Open spec items feeding this (tracked in IGC-ENCODING-DERIVATION.md)
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- op-0x2c edge exact semantics (winding rule) — affects M1 fidelity.
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- TXDN io-port texel stream — gates M3.
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- The texz coordinate-seed op + the real ramp tables — purity for M2 images.
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