CydandClaude Fable 5
2c29bf928d
The production image's VWETEST diagnostic suite provides a clean,
game-independent render harness. FLYK (VGLTEST, 32rtm build, newer
token-based sync) + clear.scn drives the ENTIRE VPX protocol through
the emulated board with zero errors: boot, iserver handshake, i860
download, token sync, scene build, draw_scene, frame-ack, clean exit
('Exiting rendering'). This validates the VPX emulation for an
arbitrary DPL renderer, not just the game.
Notes: the CYCLE flyk is a DOS/4GW build using the OLDER DPL3-style
velocirender_sync (action-check) and needs separate handling; the
VPX/DBE0151 iserver board test + reference TGAs are a future
golden-image validation avenue.
Adds RENDER-HARNESS.md and harness configs (flyk/cycle/alpha1).
Next (Phase 3): flyk DIVRGB.SCN color bars -> decode FIFO geometry
(same DIV-BIZ2 formats as restoration/divformats.py) -> OpenGL.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
27 lines
417 B
Plaintext
27 lines
417 B
Plaintext
[sdl]
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output=opengl
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[dosbox]
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memsize=32
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machine=svga_s3
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[cpu]
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core=normal
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cputype=pentium
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cycles=20000
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[serial]
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serial1=directserial realport:COM1
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serial2=disabled
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[autoexec]
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mount c "C:\VWE\TeslaRel410\ALPHA_1"
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c:
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cd \REL410\BT
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set VIDEOFORMAT=svga
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set BLASTER=A220 I5 D1 H5 P330 T6
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set TEMP=c:\
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call setenv.bat r s n n
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call showenv.bat
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32rtm.exe -x
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btl4opt.exe -egg test.egg
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32rtm.exe -u
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echo ALPHA1-RUN-DONE
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pause
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