CydandClaude Fable 5
f236d15d51
The VPX responder device now drives production BattleTech v4.10 through the full transputer/i860 boot, far past the Phase 1 wall: - iserver boot handshake solved: feeds 3 well-formed 'version' (tag 42) iserver requests, satisfying startup_handshake()'s 3 transactions. - i860 download solved: parses the outbound framed renderer messages (vr_860args/code/data/bss) and absorbs them, staying byte-aligned. - echo-action reply model validated against board source (VRENDER/VR_REMOT.C reply() echoes the received action); device tracks and echoes the last outbound action generally. Remaining sub-protocol identified and characterized: after i860 boot the host switches to a FIFO fast path (OUTSW.ASM: 0x40 tag + REP OUTSW 16-bit words to FIFO port 0x154/0x155, gated by ok_to_fifo at 0x160). The current build stops at velocirender_sync because the device only implements the slow byte path. PHASE2-PROGRESS.md documents the exact next steps (FIFO transport + render loop -> Phase 3 OpenGL backend). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
89 lines
4.7 KiB
Markdown
89 lines
4.7 KiB
Markdown
# Phase 2 — Boot Protocol Emulation: Progress
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**Status: substantial progress; boot handshake + i860 download solved; render
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transport (FIFO fast path) identified as the remaining sub-protocol.**
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The VPX device (`vpx-device/vpxlog.cpp`, env `VPX_RESPOND=1`) now drives the
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production **BattleTech v4.10** (ALPHA_1 image) through the entire transputer/i860
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boot sequence — far past the Phase 1 wall — and reaches the live renderer
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protocol. Each layer below was solved by reading the normative sources on the
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drive (`sda4/DPL3/VR_COMMS.C`, `DPL_HOST.C`, `VRENDER/VR_REMOT.C`, `LINKIO.C`,
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`OUTSW.ASM`) and iterating against the running binary.
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## Solved
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### 1. iserver boot handshake
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After the monitor (`VRENDMON.BTL`) download, `boot_xputer()` calls
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`startup_handshake()`, which does **3 iserver transactions** (Phil's comment in
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`VR_COMMS.C`: "the C run-time boots up and does 3 iserver transactions"). Each
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is a `receive_protocol()` read of a 4-byte little-endian length/route word
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(bit31=iserver, low16=payload length) + payload, answered by `iserver_action()`;
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only success is checked. The device feeds **3 well-formed iserver "version"
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requests** (tag 42, no request-content dependency) and the handshake completes.
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### 2. i860 renderer download
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`boot_860()` then streams the i860 image (`VRNOSTEX.MNG`) as framed renderer
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messages on the slow byte path: `vr_860args` (21), `vr_860code` (18, ×118),
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`vr_860data` (19, ×37), `vr_860bss` (20, ×9). The device parses the outbound
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frame stream (`[length_word:4][action:4][data]`, `nb = length_word & 0xffff`)
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and absorbs them, staying byte-aligned throughout.
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### 3. The echo-action reply model (validated against board source)
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Renderer request/reply calls (`velocirender_create`/`delete`/`flush`/`sync` in
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`DPL_HOST.C`) send an action and require the **same action echoed back**. The
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board side confirms this exactly: `VRENDER/VR_REMOT.C remote_velocirender()`
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replies with its `data` buffer whose first word is still the received action
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(`reply()` → `dN_send`). The device tracks the last outbound action and echoes
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it; this is the general model for every render call, not a one-off.
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## The remaining sub-protocol: the FIFO fast path
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After the i860 boots, the host stops using the slow byte path and switches to a
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**FIFO fast path** for the render protocol. This is why the current build still
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stops at `velocirender_sync` — the device only implements the slow path
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(0x150–0x153).
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Discovered mechanics (from the capture + `OUTSW.ASM` + `LINKIO.C`):
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- The VPX board is **dual-register**: beyond the C012 slow link
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(0x150 inputData / 0x151 outputData / 0x152 inputStatus / 0x153 outputStatus),
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there is a **FIFO data port** reached at **0x154/0x155** (observed) and an
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`ok_to_fifo` status at **0x160**.
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- `send_FIFO_protocol()` / `velocirender_transmit()` (when `use_fifo`) call the
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assembly `outsw()` (`OUTSW.ASM`): it writes a `0x40` "use fifo" tag byte, then
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`add dx,3` and `REP OUTSW` — pumping the message as **16-bit words** into the
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FIFO port. In the capture these land as alternating byte writes to 0x154/0x155
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and decode to the init/args string (e.g. `/device~0x150~/video~svga~…`).
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- The host switches to `use_fifo` once the board asserts `ok_to_fifo`
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(`fifo_ok_status()` reads 0x160 bit0); see the commented wait loop in
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`boot_xputer()`.
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### Next step (concrete)
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Extend the device to implement the FIFO transport:
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1. Answer `ok_to_fifo` (0x160 bit0) at the right time so the host enables `use_fifo`.
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2. Accept FIFO writes: the `0x40` tag, then word-stream data at the FIFO port
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(0x154/0x155). Reassemble into `[length_word][action][data]` messages
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(same framing as the slow path).
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3. Serve FIFO reads for replies: `velocirender_receive()` in FIFO mode reads the
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reply (length_word + `[action][node]`) from the FIFO/status ports. Echo the
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sent action (model already validated), returning meaningful node handles for
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`vr_create` so later `vr_delete`/geometry ops have valid remotes.
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4. Then the render loop (`vr_draw_scene` + frame-ack, `velocirender_frameack()`)
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— the Phase 3 boundary, where geometry/material/texture commands can be
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decoded into the OpenGL backend (formats already implemented in
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`restoration/divformats.py`).
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## Reproduce
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```
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set VPXLOG=C:\VWE\TeslaRel410\emulator\vpxresp.txt
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set VPX_RESPOND=1
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emulator\src\src\dosbox-x.exe -conf emulator\respond.conf
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```
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Console progression now: `BattleTech v4.10` → `BTL4Application` → RIO check →
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(handshake, i860 download succeed) → `unexpected action N in velocirender_sync`
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(the FIFO-path render handshake, the next target). The log's `#` note lines
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trace the device's decisions (handshake requests fed, frames parsed, actions
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echoed, mystery ports resolved to 0x154/0x155).
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