CydandClaude Fable 5
9a12b779bb
Disassembly confirmed the bench theory: the no-ACK wait loop at $D9E0 self-clocks in byte times (each tick transmits an IDLE keep-alive and re-enters on its TX-complete interrupt), so raising the baud silently shrank the ACK grace from ~5.2ms to ~1.6ms - under USB turnaround, hence the v1 retry storm. --widen-ackwait (requires --baud31250) sets the limit to 40 ticks (~12.8ms at 31250). v2 image: 25 bytes changed, sha256 420d4cfc...; re-disasm diff vs v1 is exactly the CMPA operand. v1/classic hashes reproduce unchanged. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
101 lines
4.5 KiB
Python
101 lines
4.5 KiB
Python
#!/usr/bin/env python3
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"""Apply the RIO v4.2 reply-wedge fix to RIOv4_2.bin -> RIOv4_2_patched.bin.
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Fix (see RIOv4_2-ANALYSIS.md): clear the reply-in-progress latch $2521 on
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EVERY reply teardown, not just the $2522-gated success path.
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1. Give-up path: redirect $D9DD `JMP $DA2F` to a stub at free ROM $DFF0
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that clears $2521/$2522 then continues to $DA2F.
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2. Success path: make $DA00's clear of $2521/$2522 unconditional.
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With --baud31250, additionally retune the SCI from 9600 to 31250 baud
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(-> RIOv4_2_patched_31250.bin): the init at $D62A loads BAUD ($102B) with
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$30 (prescale /13, divider /1 -> 2MHz E / (16*13) = 9615). $02 selects
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prescale /1, divider /4 -> 2MHz / (16*4) = 31250 exactly. One operand
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byte at $D62B. NOTE: 31250 is a non-standard rate — FTDI-class USB
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adapters produce it exactly; classic 16550 UARTs cannot. The native
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games still expect 9600, so a 31250 chip is bench/RIOJoy-only until the
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games are patched.
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Each edit asserts the exact original bytes first, so a wrong assumption
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aborts instead of corrupting the image. Address == file offset.
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"""
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import sys, hashlib
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BAUD31250 = "--baud31250" in sys.argv
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WIDEN_ACKWAIT = "--widen-ackwait" in sys.argv
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assert not WIDEN_ACKWAIT or BAUD31250, \
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"--widen-ackwait only makes sense with --baud31250 (the wait is byte-scaled)"
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args = [a for a in sys.argv[1:] if not a.startswith("--")]
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SRC = args[0] if len(args) > 0 else "RIOv4_2.bin"
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DST = args[1] if len(args) > 1 else (
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"RIOv4_2_patched_31250v2.bin" if WIDEN_ACKWAIT else
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"RIOv4_2_patched_31250.bin" if BAUD31250 else "RIOv4_2_patched.bin")
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d = bytearray(open(SRC, "rb").read())
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assert len(d) == 0x10000, f"expected 64KB image, got {len(d)}"
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orig_sha = hashlib.sha256(d).hexdigest()
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assert orig_sha == "60a88718835c654b6135dbec7721c40ef99dca07df2ad4b57eedeb24037a5f73", \
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f"unexpected source image {orig_sha}"
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def patch(addr, expect, new):
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got = bytes(d[addr:addr+len(expect)])
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assert got == bytes(expect), (
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f"@${addr:04X}: expected {got.hex()} to be {bytes(expect).hex()}")
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assert len(new) == len(expect), "length mismatch"
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d[addr:addr+len(new)] = bytes(new)
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# --- edit 1: give-up path redirect ---------------------------------------
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# $D9DD 7E DA 2F JMP $DA2F -> 7E DF F0 JMP $DFF0
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patch(0xD9DD, [0x7E, 0xDA, 0x2F], [0x7E, 0xDF, 0xF0])
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# stub at $DFF0 (was erased $FF): CLR $2521; CLR $2522; JMP $DA2F
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patch(0xDFF0, [0xFF]*8,
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[0x7F, 0x25, 0x21, # CLR $2521
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0x7F, 0x25, 0x22, # CLR $2522
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0x7E, 0xDA]) # JMP $DA2F (hi + first target byte)
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patch(0xDFF8, [0xFF], [0x2F]) # JMP low byte
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# --- edit 2: success teardown, unconditional clear -----------------------
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# $DA21 B6 25 22 LDAA $2522
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# $DA24 81 01 CMPA #$01
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# $DA26 26 06 BNE $DA2E
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# $DA28 7F 25 21 CLR $2521
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# $DA2B 7F 25 22 CLR $2522 (13 bytes $DA21-$DA2D; $DA2E RTS untouched)
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# -> CLR $2521 ; CLR $2522 ; NOP x7
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patch(0xDA21,
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[0xB6,0x25,0x22, 0x81,0x01, 0x26,0x06, 0x7F,0x25,0x21, 0x7F,0x25,0x22],
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[0x7F,0x25,0x21, 0x7F,0x25,0x22, 0x01,0x01,0x01,0x01,0x01,0x01,0x01])
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assert d[0xDA2E] == 0x39, "RTS at $DA2E must be intact"
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# --- edit 3 (--baud31250 only): SCI 9600 -> 31250 --------------------------
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# $D62A 86 30 LDAA #$30 (SCP=/13, SCR=/1) -> 86 02 (SCP=/1, SCR=/4)
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# then STAA $102B (BAUD). 2MHz E-clock: 2e6/(16*13)=9615 -> 2e6/(16*4)=31250.
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if BAUD31250:
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assert d[0xD62A] == 0x86 and bytes(d[0xD62C:0xD62F]) == bytes([0xB7,0x10,0x2B]), \
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"expected LDAA #imm ; STAA $102B at $D62A"
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patch(0xD62B, [0x30], [0x02])
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# --- edit 4 (--widen-ackwait, 31250 only): reply ACK-wait 4 -> 40 ticks -----
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# The no-ACK wait loop at $D9E0 self-clocks in BYTE TIMES: each tick transmits
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# an IDLE ($FF) keep-alive and re-enters on that byte's TX-complete interrupt.
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# 4 ticks = ~5.2ms at 9600 (USB ACK wins) but ~1.6ms at 31250 (USB loses ->
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# retry storm; bench 2026-07-18: framing 5655, Abandon 65). $28 = 40 ticks
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# = ~12.8ms at 31250, clearing FTDI worst-case turnaround with margin.
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# $D9E6 81 04 CMPA #$04 -> 81 28 CMPA #$28
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if WIDEN_ACKWAIT:
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assert d[0xD9E6] == 0x81 and bytes(d[0xD9E3:0xD9E6]) == bytes([0xB6,0x31,0x7B]), \
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"expected LDAA $317B ; CMPA #imm at $D9E3"
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patch(0xD9E7, [0x04], [0x28])
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open(DST, "wb").write(d)
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new_sha = hashlib.sha256(d).hexdigest()
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# byte-diff report
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diffs = [(a, orig, d[a]) for a, orig in
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enumerate(open(SRC,"rb").read()) if d[a] != orig]
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print(f"source : {SRC} sha256 {orig_sha}")
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print(f"patched: {DST} sha256 {new_sha}")
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print(f"{len(diffs)} bytes changed:")
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for a, o, n in diffs:
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print(f" ${a:04X}: {o:02X} -> {n:02X}")
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