Comprehensive VWE Video Display/splitter Board writeup: what it is (dumb ISA
splitter tapping the companion Cirrus Logic SVGA feature connector), the
definitive I/O register map from L4SVGA16.ASM (Secondary 0x302 / Aux1 0x30A /
Aux2 0x312, each +0 mask/+1 read/+2 write/+3 data, 6-bit DAC; clock divider
0x319 off / 0x31A on), the byte-lane split (low byte->Secondary, high
byte->Aux1/Aux2 -> separate VGA heads -> octopus cable -> 5 mono MFDs + color
radar), the driver's bitMask+channelEnable CLUT-build trick that packs multiple
displays into one framebuffer, the pixel-mask flash + Secondary-only fade, our
emulation, the OPEN RP decode problem, and a physical-sample verification
checklist (port-decoder PAL, 3 RAMDACs, octopus pinout, Cirrus chip id).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
CydandClaude Fable 5
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