Files
TeslaRel410/emulator
CydandClaude Opus 4.8 9f6cd44333 i860 emu: pfgt/pfle exact semantics (R bit selects gt/le, pipelined retire+advance); IGC consumption resets page write-index for reuse
- pfgt/pfle/pfeq are always pipelined: fdest <- A-pipe retire, push undefined;
  bit7 selects pfle (inverted CC sense) -- was misread as result precision.
  316 pipelined compares in the firmware previously desynced the A-pipe.
- h_igcwait now models full consumption: done-status nonzero AND write-index
  reset (+0x7f8=0), otherwise queue pages saturate at 0x7f0 across frames and
  enqueueing silently stops (observed: even the per-frame marker item stopped
  binning by cmd ~4300).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-15 21:05:08 -05:00
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